Method and device for coding binary data and a device decoding coded data

A device for preparing an input signal for transmission, said input signal having a sequence of groups selected from a set of all possible groups, each of said groups having n binary digits having a repetition frequency of F, comprising:

• a parallel-read series-write memory register having one input for receiving the input signal and n outputs for delivering simultaneously the n bits of each group;
• first memory means having n address inputs coupled respectively to the n outputs of said memory register and 2n outputs for delivering respectively, one word of an associated pair of a plurality of pairs of words, each of said pairs being uniquely associated with one possible output of said memory register, respectively, each of said words having n bits of a "0" state and n bits of a "1" state and a repetition frequency of 2F, each of the bits of said words being adjacent to a bit having the same state except end bits of said words which can be adjacent to a bit in said word of opposite state, one word of each of said pairs being a complement of the other word of each of said pairs;
• a first parallel-read/write memory register means having 2n inputs coupled to the outputs of said first memory means for storing the value of the word delivered by said first memory means, said first memory register means having 2n outputs;
• an inverter having 2n inputs coupled respectively to the 2n outputs of said first memory register means, a control input for receiving a control signal, and 2n outputs;
• a second parallel-read/write memory register means having 2n inputs coupled respectively to the 2n outputs of said inverter and 2n outputs;
• a control device having one output for delivering said control signal for said inverter as a function of both the binary word defined by the 2n bits present on the 2n inputs of the inverter and the binary word defined by the 2n bits present on the 2n outputs of said inverter;
• and
• a series-read parallel-write memory register having 2n inputs coupled respectively to the 2n outputs of said second memory register means and one output.