Dynamic divider circuit
AssigneeKabushiki Kaisha Suwa Seikosha
InventorShinji Morozumi
Life of this patent
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Abstract
A dynamic divider circuit comprised of insulating gate field effect transistors and capable of operation using minimal current consumption in a reduced space is provided. Master and slave multiple inverters and an intermediate inverter are formed from complementary connected P-channel and N-channel insulated gate field effect transistors, the master and the slave inverter being directly coupled to the master inverter. The coupling of the master, intermediate, and slave inverters providing reduced current consumption and a more simplified circuit by utilizing the parasitic capacitance of said field effect transistors as a memory.
Claims17
A dynamic binary divider circuit comprised of an intermediate inverter, a first multiple inverter and a second multiple inverter, said intermediate inverter being formed by the complementary connection of a P-channel transistor and an N-channel transistor, each said first and second multiple inverters being formed from the serial connection of two-series-connected P-channel transistors to two series connected N-channel transistors respectively, the drain terminals of one of the P-channel and N-channel transistors of each multiple inverter being connected together to define an output terminal of the respective multiple inverter, the gate terminals of said one of the P-channel and N-channel transistors of each multiple inverter being connected together to define an input terminal of the respective inverter, said output terminal of said first multiple inverter being coupled through said intermediate inverter to the input of said second multiple inverter, the output terminal of said second multiple inverter being coupled to the input terminal of said first multiple inverter, the other P-channel transistor of said first multiple inverter and the other N-channel transistor of said second multiple inverter being connected for receipt at the respective gate terminals thereof with a first clock pulse and the other N-channel transistor of said first multiple inverter and the other P-channel transistor of said second multiple inverter being connected for receipt at the respective gate terminals thereof with a second clock pulse which is the complement of said first clock pulse whereby the parasitic capacitance at respective outputs of said first and second multiple inverters is utilized as a memory means, so that a division of said clock pulse applied is effected.
A dynamic divider circuit for use in an electronic timepiece comprising a master inverter, a slave inverter, and an intermediate inverter, said master and slave inverters each including first and second serially connected P-channel field effect transistors and first and second N-channel serially connected transistors, the second N-channel and P-channel transistors of each of said master and slave inverters being complementary coupled so as to define master and slave inverter output terminals and a master and slave inverter input terminal, the respective gate terminals of the first N-channel transistor of said master inverter and the first P-channel transistor of said slave inverter are connected to receive a first clock pulse .phi. having a first frequency, the respective gate terminals of the first P-channel of said master inverter and the first N-channel transistor of said slave inverter connected to receive a second clock pulse .phi. which is the complement of said first clock pulse, the output of said master inverter producing a signal M having a second frequency equal to one-half said first frequency, said master inverter being coupled through said intermediate inverter to produce a complementary input M for application to said slave inverter, and the output of slave inverter being a frequency equal to said second frequency but delayed by a period equal to one-half the period of first clock pulse .phi., applied to the input of said master inverter, whereby the parasitic capacitance at the common output terminals of said master and slave inverters is utilized as a memory means, the leakage current and the effective capacitance determining the operating frequencies of said divider.
The combination comprising, first and second selectively operative inverting means, each inverting means having a signal input terminal, a power input terminal means and an output;
- an inverter having an input connected to said output of said first inverting means, and having an output connected to said signal input terminal of said second inverting means;
- means connecting said output of said second inverting means to said signal input terminal of said first inverting means;
- and means for applying control signals to the power input terminal means of said first and second inverting means to render operative said first inverting means and render inoperative said second inverter during one time interval and for rendering inoperative said first inverting means and rendering operative said second inverting means during another time interval.
The combination comprising, first and second selectively operative inverter means each having an input and an output;
- a continuously operative inverter having an input coupled to said output of said first inverter means, and having an output coupled to said input of said second inverter means;
- means coupling said output of said second inverter means to said input of said first inverter means;
- and means for rendering operative one of said first and second inverter means at a time.
The combination comprising, two power terminals for the application therebetween of an operating potential;
- first and second inverting means connected in parallel between said two power terminals;
- each inverting means having an input and an output and including a first switch means connected in series with a first controllable conduction means between one of said power terminals and said output and including a second switch means connected in series with a second controllable conduction means between the other one of said power terminals and said output;
- an inverter having an input and an output, the input of said inverter being connected to the output of said first inverting means and the output of said inverter being connected to the input of said second inverting means;
- means connecting the output of said second inverting means to the input of said first inverting means;
- and means for applying signals to said switch means for during one time interval closing the two switch means of said first inverting means and opening the two switch means of said second inverting means and for during a second succeeding time interval opening the two switch means of said first inverting means and closing the two switch means of said second inverting means.
Dependencies are inferred from the claim text.