Method of making silicon-on-sapphire FET
AssigneeGeneral Electric Company
InventorsWilliam R. Cady, SePuan Yu, John R. Eshbach
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Abstract
Junction and metal-semiconductor field effect transistors have a sapphire substrate to realize isolation and reduced capacitance, and have a self-aligned gate to minimize source parasitic resistance. A lightly doped, opposite conductivity type region under the channel forces carriers to flow near the silicon surface where mobility is high; this region is depleted at all times by the P-N junction built-in voltage and acts as an insulator. These devices serve as switches in high speed logic applications and as microwave amplifiers.
Claims3
The method of making a silicon-on-sapphire junction field effect transistor structure comprising the steps of:
- forming on a sapphire substrate lower and upper opposite conductivity type silicon layers having given area dimensions, said lower layer being lightly doped and said upper layer moderately doped;
- depositing on said upper silicon layer a layer of doped polycrystalline silicon and fabricating thereon a patterning layer;
- etching said polycrystalline silicon to undercut beneath said patterning layer and define a gate conductor;
- implanting impurity ions into exposed areas of said silicon layers using said patterning layer as a mask, and removing the latter;
- annealing to activate said implanted impurity ions and result in heavily doped source and drain regions which are self-aligned with said gate conductor and have a channel region therebetween, said annealing further diffusing impurity atoms from said polycrystalline silicon gate conductor to create a gate region of opposite conductivity type as said channel region;
- and
- depositing conductor metallizations on said source and drain regions.
The method of making a silicon-on-sapphire metal-semiconductor field effect transistor structure comprising the steps of:
- forming on a sapphire substrate a lower P-type and an upper N-type silicon layer having given area dimensions, said lower layer being lightly doped and said upper layer moderately doped;
- depositing on said upper silicon layer a layer of metal and fabricating thereon a patterning layer;
- etching said metal layer to undercut beneath said patterning layer and define a gate conductor;
- implanting impurity ions into exposed areas of said silicon layers using said patterning layer as the mask, and removing the latter;
- annealing to activate said implanted impurity ions and produce heavily doped source and drain regions which are self-aligned with said gate metal and have a channel region therebetween, said annealing further forming a Schottky barrier at the gate metal-channel interface;
- and
- depositing conductor metallizations on said source and drain regions.
Dependencies are inferred from the claim text.