Loop switching system
AssigneeBell Telephone Laboratories, Incorporated
InventorRichard F. Cantwell, Jr.
Life of this patent
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Abstract
The loop switching system of this invention overcomes the problems of prior art loop switching systems by providing dynamic rearrangeability of loop switching systems. In particular, the subject loop switching system is comprised of a number of port circuits or nodes serially connected together to form one or more loops. The interconnection of these various ports into one or more loops is implemented on a dynamic basis by means of a central switching matrix.
Claims15
A communication system for serially interconnecting n communication circuits (T1-Tm, ST(n-m)-Stn) comprising:
- n port means (103-1 to 103-n), each having an input (SDI-i) and an output terminal (SDO-i), associated on a one-to-one basis with said n communication circuits (T1-Tm, ST(n-m)-STn) for interfacing said n communication circuits (T1-Tn, ST(n-m)-STn) to said communication system;
- control means (101) for establishing an order of interconnection for all of said n port means;
- and
- interconnection means (100) connected to said input (SDI-i) and said output (SDO-i) terminals of all of said n port means (103-1 to 103-n) and responsive to said control means (101) for carrying data messages from said output terminal (SDO-(m+1)) of the (m+1)th port means (103-(m+1)) to said input terminal (SDI-m) of the m th port means (103-m) for all n said port means (103-1 to 103-n) according to said order of interconnection.
A communication system for serially interconnecting n communication circuits (T1-Tm, ST(n-m)-STn) comprising:
- n port means (103-1 to 103n), each having an input (SDI-i) and an output terminal (SDO-i), associated on a one-to-one basis with said n communication circuits (T1-Tm, ST(n-m)-STn) for interfacing said n communication circuits (T1-Tm, ST(n-m)-STn) to said communication system;
- control means (101) for establishing an order of interconnection for all of said n port means (103-1 to 103-n);
- interconnection means (100) connected to said input (SDI-i) and said output (SDO-i) terminals of all of said n port means (103-1 to 103n) and responsive to said control means (101) for carrying data messages from said output terminal (SDO-(m+1)) of the (m+1) th port means (103(m+1)) to said input terminal SDI-(m) of the m th port means (103-m for all said n port means (103-1 to 103-n) according to said order of interconnection;
- clock means (604) connected to each of said n port means (103-1 to 103-n) for generating control and timing signals to define time slot intervals;
- and
- wherein each of said n port means (103-(m+1)) is responsive to said control and timing signals for transmitting a single bit of said data message to the subsequent one of said n port means (103-m) via said interconnection means (100) during each of said time slot intervals.
Dependencies are inferred from the claim text.