Address buffer circuit
AssigneeFujitsu Limited
InventorHiroshi Shimada
Life of this patent
Estimating the term…
Abstract
An address buffer circuit which generates a pair of complementary signals for selecting a memory cell according to an address input signal is disclosed. This address buffer circuit comprises a short circuit device connected between a pair of output terminals for the complementary signals. During the stand-by period of a memory, the short circuit device electrically connects the pair of output terminals, so that the potential of both of the pair of output terminals becomes an intermediate level between high and low levels provided at the output terminals during the active period of the memory.
Claims13
An address buffer circuit, having an active period which has high and low levels and having a standby period, which generates a pair of complementary output signals corresponding to an address input signal, comprising:
- buffer circuit means for buffering the address input signal;
- means, operatively connected to said buffer circuit means, for suspending power consumption by said address buffer circuit when in the stand-by period responsive to an external signal;
- output means, operatively connected to said buffer circuit means, having a par of output terminals for outputting said pair of complementary output signals;
- and
- short circuit means, operatively connected between said pair of output terminals of said output means, for forcing the potential of said pair of output terminals to a same potential between the high and low levels of said address buffer circuit in the active period by electrically connecting said pair of output terminals in said stand-by period.
An address buffer circuit, operatively connectable to receive an external address signal and an external chip select signal and having a stand-by period, comprising:
- address and buffer means, operatively connectable to receive the external address signal and the external chip select signal, for generating first and second internal address signals at first and second output terminals, respectively, responsive to the external address signal and the external chip select signal;
- and
- short circuit means, operatively connected between the first and second output terminals of said address and buffer means and operatively connectable to receive the external chip select signal, for connecting the first and second output terminals together responsive to the external chip select signal, so that the first and second output terminals are held at the same level, the first and second internal address signals are at the same level and power consumption by said address buffer circuit is suspended when in the stand-by period.
An address buffer circuit operatively connectable to receive an external chip select signal, comprising:
- address means for generating first and second internal address signals, said address means comprising:
- a push-pull circuit producing outputs;
- and
- a power down transistor operatively connected to said push-pull circuit, operatively connectable to receive the external chip select signal and being controlled by the external chip select signal;
- and
- short circuit means, operatively connected to said-push-pull circuit and operatively connectable to receive the external chip select signal, for forcing the outputs of said push-pull circuit to a same potential level and being controlled by the external chip select signal.
Dependencies are inferred from the claim text.