Monolithically integrated semiconductor memory with dummy and charge equalization cells

Abstract

Monolithically integrated semiconductor memory having a matrix formed of identical information storage cells arranged in rows and columns in the form of single-transistor storage cells, a respective comparator and a dummy cell, likewise provided by a single-transistor storage cell, being operatively associated either with each matrix column or each matrix row, including a respective second single-transistor storage cell provided as a charge equalization cell and identical, at least with respect to storage capacity with the dummy cell and operatively associated with each of the dummy cells, each of the charge equalization cells respectively having a drive balanced relative to the drive of the dummy cell operatively associated therewith so that, in a first phase triggered by the respective dummy cell having been addressed by an addressing signal, the dummy cell storage capacity is charged and the charging state of the storage capacity of the respective charge equalization cell is set so that the charging state in the charge equalization cell corresponds to the signal inverse to the addressing signal effecting the charging of the dummy cell, so that, in a second operating phase, the storage capacity of the dummy cell and the storage capacity of the charge equalization cell are connected in parallel for charge equalization, and so that, in a third operating phase, the respective storage capacities of the dummy cell and the charge equalization cell are again separated by driving the comparator from the dummy cell.

Dependencies are inferred from the claim text.