Semiconductor memory circuit

A semiconductor memory circuit comprising:

• a right memory cell group and a left memory cell group, each having a plurality of rows and columns corresponding to word lines and bit lines, respectively;
• a plurality of word decoders respectively connected to corresponding ones of said rows, said word decoders being connected between the right and left memory cell groups and receiving row address signals specifying a word line within the memory cell group to be selected;
• and
• a plurality of column decoders correspondingly connected to respective ones of said columns for receiving column address signals specifying the bit within the memory cell group to be selected;
• a plurality of right memory cell group selection and drive gates operatively connected between respective ones of said word decoders and respective ones of said rows connected to said right memory cell group;
• a plurality of left memory cell group selection and drive gates operatively connected between respective ones of said word decoders and respective ones of said rows connected to said left memory cell group;
• and
• discriminating means for discriminating whether the memory cell to be selected is located in the right or left memory cell group, for providing an output responsive to said discriminating means, and for controlling the right and left memory cell group selection and drive gates in accordance with the output of said discriminating means.