Chip topography for integrated circuit communication controller

An integrated circuit chip for use in a data processing system which includes a processor and a plurality of remote devices in which the processor will output a plurality of first and second control signals enabling data signals to be transmitted between the processor and the remote devices, said circuit chip comprising in combination:

• a plurality of input and output transmission wires connected to said remote devices over which data signals are transmitted;
• first control means receiving data signals from the processor for transmitting the data signals over said output transmission wires to a remote device;
• second control means receiving data signals from a remote device over said input transmission wires for transmitting the received data signals to the processor;
• first register means connected to the processor for storing said first and second control signals for generating a plurality of third control signals selecting a first or second clock frequency, a fourth control signal selecting the number of data signals transmitted between the processor and the remote devices and a timing control signal in response to the storing of said first and second control signals;
• means connected to said first register means for generating a plurality of clock signals at a first or second timing frequency in accordance with the third control signals received from said first register means;
• first bus means connected to said first register means over which said first, second, third, and fourth control signals and said timing control signal are transmitted;
• said first control means includes first logic circuit means for transmitting data signals from said processor and the selected clock signals to one of said remote devices;
• said second control means includes second logic circuit means for transmitting the generated clock signals to the remote device enabling the data signals to be transmitted from the remote device to the processor;
• said integrated circuit chip having first, second, third and fourth sequentially located edges;
• said first and second control means being located substantially closer to said third edge than to said first edge;
• said first and second logic circuit means being located substantially closer to said first edge than to said third edge;
• said bus means being located substantially in the middle of the chip and extending in a direction parallel to said first and third edges;
• and
• said signals generating means being located substantially closer to said first edge than to said third edge.