Data recovery method and apparatus using variable window

A method for recovering encoded digital information from a serialized bit stream wherein an information encoding scheme is employed having state amplitude deviations capable of occurring at two distinguishable positions relative to synchronizable bit cell timing units of nominally constant duration, the method comprosing the steps of:

• providing first and second types of detection windows, each window of said first type being nominally centered within a corresponding bit cell timing unit and each window of said second type being nominally centered on a transition between adjacent bit cell timing units;
• registering as a valid first value each occurrence of said state amplitude deviation occurring within said first type of detection window;
• registering as a valid second value each occurrence of said state amplitude deviation occurring within said second type of detection window;
• and
• after registering a valid first or second value, and if a further valid value has not subsequently occurred before a defined time during a second said detection window of the same type extant during the registering of a valid value, contracting said second detection window of the same type at its trailing edge and expanding the second subsequent one of said detection windows of the other type at its leading edge.

In an apparatus for recovering information from a serialized bit stream by employing framing windows to distinguish between nominally synchronized bits in said bit stream and a device for varying the duration of selected recovery windows in response to the position of actual input bits from said bit stream relative to a prescribed position within a bit cell timing unit, said device comprising:

• a first counter for counting said recovery windows;
• a second counter for tracking the bit position of bits of said serialized input bit stream relative to a bit cell timing unit;
• an arithmetic means having inputs coupled to outputs of said first counter and outputs of said second counter and outputs coupled to inputs of said second counter, said arithmetic means operative to preload a position signal to said second counter in response to selected input codes to said arithmetic means;
• a latch means having inputs coupled to selected output positions of said arithmetic means and outputs coupled to selected input positions of said arithmetic means for modifying selected input address instructions to said arithmetic means according to the output coding from said arithmetic means;
• a window latch means coupled to an output of said second counter means, which output is indicative of completion of a window cycle;
• and
• a circuit means for synchronizing operation of said first and second counters and said latch means.