Memory mapping system
AssigneeTektronix, Inc.
InventorJohn Lewis
Life of this patent
Estimating the term…
Abstract
A circuit for enhancing the performance of a random-access-memory-based memory expansion system is disclosed. Memory capacity and a control register are added to the traditional memory mapping circuit. The increased memory is utilized to store several maps simultaneously and the circuit output is then switched from one stored map to another according to data present at the control register outputs. Thus, by pre-loading the circuit with all the memory maps required by a particular program, delay caused by map changes is reduced to the time required to move data to the control register outputs.
Claims10
A memory mapping system comprising:
- a first address bus portion having a first set of n lines and a second set of x lines, for receiving logical address information;
- a second address bus portion for providing physical address information to main memory means of a computer, said second address bus portion having a first set of N lines, where N is greater than n, and a second set of x lines connected to the second set of x lines of the first address bus portion;
- random access memory means having n input lines connected to the first set of n lines of the first address bus portion and N output lines connected to the first set of N lines of the second address bus portion, said random access memory means having a plurality of memory regions which are individually selectable for connection to said n input lines and to said N output lines, and each memory region being operative, when selected, to transform information provided on said n input into information on said N output lines;
- and
- a control register having input means for receiving data and output means at which said data is made available and operatively connected to the random access memory means for utilizing said data to select which one of the plurality of memory regions is connected to said n input lines and to said N output lines.
A memory mapping system comprising:
- a first address bus portion having a first set of n lines and a second set of x lines, for receiving logical address information;
- a second address bus portion for providing physical address information to main memory means of a computer, said second address bus portion having a first set of N lines, where N is greater than n, and a second set of x lines connected to the second set of x lines of the first address bus portion;
- and
- random access memory means having n input lines connected to the first set of n lines of the first address bus portion and N output lines connected to the first set of N lines of the second address bus portion, said random access memory means being operative to transform information provided on said n input lines into information on said N output lines, and the random access memory means also having a load data input for loading data into the random access memory means, whereby the information that is provided on said N output lines in response to given information provided on said n input lines may be altered.
Dependencies are inferred from the claim text.