Synchronizing circuit for matrix television set

In a synchronizing circuit for a matrix television set having display means including picture elements arranged in a matrix of lines and columns, and connected to line driver and column driver circuits respectively so as to be individually selectable in both line and column directions, and wherein display is made by selecting lines and columns successively, the improvement therein comprising:

• a voltage controlled oscillator circuit, said oscillator circuit producing a shift clock signal applied to said column driver circuits for selecting individual columns in succession;
• first frequency divider means for dividing down an output frequency signal from said oscillator circuit, the output of said first frequency divider means being a clock signal applied to said line driver circuits for selecting individual lines in succession;
• phase comparison means, said comparison means determining the difference in phase of a output of said first frequency divider means with the phase of a horizontal synchronizing signal, said horizontal synchronizing signal being a portion of a television signal transmission, an output of said comparison means being fed back to said oscillator circuit, said feedback being in proportion to said phase difference, said oscillator circuit being adapted to adjust the output frequency of oscillation in response to said phase difference signal, said adjustment causing said phase difference to approach zero, said clock signals being synchronized with said horizontal synchronizing signal;
• a second frequency divider means, said second frequency divider means further dividing the output signal from said first frequency divider, the output of said second frequency divider means being applied to said line driver circuits so as to provide vertical synchronization of picture frames in said television transmission.