Power MOS transistor with a plurality of longitudinal grooves to increase channel conducting area

A semiconductor device comprising in combination:

• a substrate having a substantially plane first major surface;
• first and second spaced regions of a first conductivity type formed in said surface;
• a third region of a second conductivity type opposite said first conductivity type between said first and said second regions at said surface;
• a plurality of spaced groove regions in said major surface, said groove regions being separated by portions of said substrate coplanar with said first major surface, and said grooves extending into each of said first, second, and third regions;
• a thin insulating layer over said third region both in said grooves and across surface portions coplanar with said first major surface;
• and
• gate means over said insulating layer for controlling a conductive surface channel between said first and second regions in said grooves and at said first major surface.