Transfer bus matrix
AssigneeT-Bar Incorporated
InventorLewis J. Seiden
Life of this patent
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Abstract
A transfer bus matrix provides a single channel of a plurality of conductors to which multiple inputs and multiple outputs are connected by ports or control gates which allow them to be selectively interconnected by control means. Individual matrices or groups of matrices may be involved, including a multistage matrix having individual substage matrices using a transfer bus. Each matrix may be monitored by monitor means having connections to each of the conductors and a multistage matrix may be monitored in each substage and arranged so that each single input may be selectively monitored at various stages throughout the multistage matrix.
Claims20
A transfer bus matrix switching system for connecting selected input ports to selected output ports whereby multiple signals may be sequentially carried by the bus comprising:
- a bidirectional transmission line transfer bus providing a common parallel multi-line channel for all signals;
- a plurality of input bidirectional channels connected to the bus by individual gate means providing input ports;
- a plurality of output bidirectional channels connected to the bus by individual gate means providing output ports;
- and
- control means independent of the bus and input and output ports for selectively activating an input port and at least one output port contemporaneously and sequentially connecting such selected ports via the transfer bus.
A multistage matrix of three or more stages, each stage of which has a plurality of transfer bus matrix substages of the same type for connecting selected input ports of the first stage to selected output ports of the last stage whereby multiple signals may be sequentially carried on each substage transfer bus consisting of a bidirectional multi-line channel usable by all input and output ports of each substage, a plurality of input and output channels connected to each substage transfer bus by individual gate means providing substage input and output ports, and control means for each substage independent of the bus and input and output ports for selectively activating an input port and at least one output port contemporaneously and sequentially connecting such selected ports via the transfer bus for each substage.
Dependencies are inferred from the claim text.