Sample and hold circuit

A sample and hold circuit, for holding a sampled input voltage, comprising:

• an input terminal;
• an output terminal;
• a first field-effect transistor, connected between said input terminal and said output terminal, for sampling an input voltage applied to said input terminal;
• means for applying a first control voltage to the gate of said first field-effect transistor for selectively switching said first field-effect transistor between conductive and non-conductive states,
• a holding capacitor, connected to said output terminal, for holding said sampled input voltage;
• means operatively connected to the gate of said first transistor for receiving and inverting the first control voltage and outputting the inverted voltage as a second control voltage;
• a second field-effect transistor having a source and drain commonly connected to said output terminal and a gate connected to said inverting means and receiving said second control voltage for selectively switching said second field-effect transistor between non-conductive and conductive states, relative to the conductive and non-conductive states, respectively, of said first field-effect transistor, wherein the sum of the capacitance between the gate and source plus the capacitance between the gate and the drain of said second field-effect transistor is approximately equal to the capacitance between the gate and the source of said first field-effect transistor, and the area of the channel region, defined by multiplying the channel length L times the channel width W, of said second field-effect transistor is approximately equal to half of the area of the channel region of said first field-effect transistor.