Serial-to-parallel converter

A serial-to-parallel converter receiving respectively serial clock pulses, serial data bits synchronous with the serial clock pulses, a selected number of consecutive serial data bits forming a serial input word, said converter further receiving serial word synchronizing pulses synchronous with said serial input words, said converter comprising in combination:

• (a) a means for receiving said serial word synchronizing pulses and generating a parallel clock pulse in response to an integer number of serial word synchronizing pulses and synchronously therewith;
• (b) a counter means having an input for receiving said serial clock pulses and an output for synchronously providing a respective count in response to each received serial clock pulse, said counter means coupled to be reset by said parallel clock pulse;
• (c) a decoder means having an input for receiving said count provided by said counter means and having a plurality of separate outputs each coupled to provide a separate output signal in response to each count and synchronously therewith;
• (d) a plurality of output storage means each having a separate data input enable terminal coupled to one separate output of said decoder means and each having a separate data output terminal, said plurality of output storage means having interconnected data input terminals for receiving simultaneously said serial data bits and having interconnected data output enable terminals for receiving simultaneously said parallel clock pulse, respectively, each said output storage means being coupled to store one particular serial data bit received thereby coincidently with a particular separate output signal from said decoder means and said plurality of output storage means being coupled to apply simultaneously said stored data bits to said separate outputs in form of a parallel output word in response to and synchronously with receiving said parallel clock pulse.