Semiconductor memory device with decoder for chip selection/write in
AssigneeFujitsu Limited
InventorsKiyoshi Miyasaka, Mitsuo Higuchi
Life of this patent
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Abstract
A semiconductor memory device includes in its chip a decoder circuit which receives external selection signals for selecting a memory chip. The decoder circuit performs the selection of the memory chip in accordance with a logic corresponding to the combination of the external selection signals. The selection logic can be changed by the user of the semiconductor device.
Claims12
A semiconductor memory device for receiving a plurality of external selection signals in which a semiconductor memory chip of said device is selected in accordance with a predetermined combination of the external selection signals, said device comprising:
- a semiconductor memory chip;
- and
- a decoder circuit for receiving said external selection signals and provided in said semiconductor memory device, said decoder circuit selecting said semiconductor memory chip in accordance with a logic corresponding to the predetermined combination of said external selection signals, said logic capable of being changed by the user of said semiconductor memory device.
A semiconductor memory device for receiving a plurality of external selection signals, having a writing-in mode and a chip selection mode in which a semiconductor memory chip of said device is selected in accordance with a predetermined combination of the external selection signals, said device comprising:
- a semiconductor memory chip;
- a control circuit for receiving said external selection signals and producing a first output signal and its inversion in the writing-in mode and a second output signal and its inversion in the chip selection mode;
- and
- a decoder circuit for receiving said first and second output signals and their inversions for writing into said semiconductor memory chip or selecting said semiconductor memory chip;
- wherein said control circuit and said decoder circuit are provided in said semiconductor memory device, data is written into said semiconductor memory chip in response to the writing-in mode and said first output signal and its inversion to said decoder circuit, and said semiconductor memory chip is selected in response to the chip selection mode and applying said second output signal and its inversion to said decoder circuit.
A semiconductor memory device having a plurality of memory cell groups, each having selected and non-selected states, said device comprising:
- means for selecting said memory cell groups and for receiving a plurality of external memory cell select signals having a plurality of input signal combinations, each select signal having active and inactive states, said selecting and receiving means having a plurality of outputs correspondingly, connected to said plurality of memory cell groups said outputs vary selectively in response to said plurality of input signal combinations, select predetermined corresponding memory cell groups and place in the non-selected state, the remainder of said memory cell groups;
- and
- means for allowing the user of said semiconductor memory device to change said predetermined corresponding memory cell group selected in response to each one of said plurality of said input signal combinations.
A semiconductor memory device having a write-in mode and a chip selection mode, a plurality of memory cell groups each having selected and non-selected states, said device comprising:
- decoder circuit for receiving a relatively high power supply voltage and a relatively low power supply voltage, having a plurality of outputs correspondingly, operatively connected to said plurality of memory cell groups, for selecting said memory cell groups, said memory cell groups being selected in accordance with said plurality of input signal combinations;
- and,
- control circuit for receiving a relatively high power supply voltage and a relatively low power supply voltage, and for receiving external memory cell select signals having a plurality of input signal combinations, each select signal having active and inactive states comprising a plurality of input signal combinations, said control circuit having a first output signal and its inversion for application to said decoder circuit varying in response to said plurality of input combinations and said writing-in mode, and a second output signal and its inversion for application to said decoder circuit varying in response to said plurality of input signal combinations and said chip selection mode;
- and
- wherein the writing-in of data into said semiconductor memory device is enabled by said first output signal and its inversion and the selection of said semiconductor memory device is enabled by said second output signal at its inversion.
Dependencies are inferred from the claim text.