Schmidt trigger circuit
AssigneeFujitsu Limited
InventorHiroshi Hirao
Life of this patent
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AssigneeFujitsu Limited
InventorHiroshi Hirao
Estimating the term…
In a Schmidt trigger circuit for delaying a signal, means are provided to reduce an undesirable time lag in the discharge of charges stored in a node. The node of interest is connected to the gate of a feed-back transistor to supply a bias voltage to its gate. The node may be charged up to a high level by an abnormal rise of the power source level, and be held at that high level regardless of a subsequent lowering of the power source level to cause a time lag in the lowering of said high level at the time of discharging said charges stored at the node. Such delay is undesirably large. To reduce said time lag a transistor is connected between the node and the power source line such that when the level difference therebetween exceeds the threshold voltage of the transistor, the transistor is turned ON to discharge therethrough charges of the node to the power source line.
In a Schmidt trigger circuit which is provided with at least first, second and third transistors which are series-connected at their respective sources and drains between a power source line and a ground line, and a fourth transistor which has its gate connected to a first node at the series connection of the first and second transistors to apply a feedback current from the drain of said fourth transistor to a second node at the series connection of the second and third transistors, the improvement comprising
Dependencies are inferred from the claim text.