US 4,385,308 AGranted

Non-volatile semiconductor memory device

AssigneeTokyo Shibaura Denki Kabushiki Kaisha

InventorYukimasa Uchida

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Abstract

A silicon nitride layer and a memory gate electrode are successively formed over a portion of a principal surface of a semiconductor substrate between drain and source regions formed therein and adjacent to the drain region via a thin silicon dioxide layer. A portion of the substrate principal surface, to which the source region is contiguous, is covered by a thick silicon dioxide layer, and a selection gate electrode is buried in the thick silicon dioxide layer. This two-input gate transistor construction constitutes a memory cell.

Claims3

Dependent claims

A non-volatile semiconductor memory device comprising:

(a) a plurality of memory cells arranged in a matrix having rows and columns, each of said memory cells including:
(i) a semiconductor substrate of a first conductivity type,
(ii) drain and source regions of a second conductivity type opposite to said first conductivity type, said drain and source regions being formed in and contiguous to a principal surface of said semiconductor substrate such that said source and drain regions are separated in said semiconductor substrate a predetermined distance, said source regions being constituted by impurity injection layers extending continuously in the direction of said rows of said matrix and said source and drain regions capable of being used by adjacent memory cells in the direction of said columns of said matrix,
(iii) a first gate insulating film having no charge storage function and being formed on said principal surface with a thick portion and a thin portion, said thick portion covering said source region and said thin portion extending from said thick portion to the boundary of said substrate and said drain region which is closest to said source region,
(iv) a selection gate electrode buried within said first gate insulating film, said selection gate electrode including a first impurity-doped polycrystal layer extending continuously in the direction of said rows of said matrix,
(v) a second gate insulating film having a charge storage function and formed on said first gate insulating film, and
(vi) a memory gate electrode formed on said second gate insulating film having a first end portion overlapping a portion of said selection gate electrode via said second gate insulating film and said thick portion of said first gate insulating film and a second end portion overlapping said thin film portions, said memory gate electrode including a second impurity-doped polycrystal layer extending continuously in the direction of said rows of said matrix;
(b) first means for commonly connecting said selection gate electrodes and said memory gate electrodes of said individual memory cells in each of said rows;
(c) a metal lead line commonly connecting said drain regions of said memory cells in each of said columns;
and
(d) second means for commonly connecting said source regions of all of said memory cells in said matrix.

8 more elements

Dependencies are inferred from the claim text.

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Abstract

A non-volatile semiconductor memory device comprising:

(a) a plurality of memory cells arranged in a matrix having rows and columns, each of said memory cells including:
(i) a semiconductor substrate of a first conductivity type,
(ii) drain and source regions of a second conductivity type opposite to said first conductivity type, said drain and source regions being formed in and contiguous to a principal surface of said semiconductor substrate such that said source and drain regions are separated in said semiconductor substrate a predetermined distance, said source regions being constituted by impurity injection layers extending continuously in the direction of said rows of said matrix and said source and drain regions capable of being used by adjacent memory cells in the direction of said columns of said matrix,
(iii) a first gate insulating film having no charge storage function and being formed on said principal surface with a thick portion and a thin portion, said thick portion covering said source region and said thin portion extending from said thick portion to the boundary of said substrate and said drain region which is closest to said source region,
(iv) a selection gate electrode buried within said first gate insulating film, said selection gate electrode including a first impurity-doped polycrystal layer extending continuously in the direction of said rows of said matrix,
(v) a second gate insulating film having a charge storage function and formed on said first gate insulating film, and
(vi) a memory gate electrode formed on said second gate insulating film having a first end portion overlapping a portion of said selection gate electrode via said second gate insulating film and said thick portion of said first gate insulating film and a second end portion overlapping said thin film portions, said memory gate electrode including a second impurity-doped polycrystal layer extending continuously in the direction of said rows of said matrix;
(b) first means for commonly connecting said selection gate electrodes and said memory gate electrodes of said individual memory cells in each of said rows;
(c) a metal lead line commonly connecting said drain regions of said memory cells in each of said columns;
and
(d) second means for commonly connecting said source regions of all of said memory cells in said matrix.

8 more elements