Back to results
US 4,384,300 AGranted
Negative resistance device
AssigneeTokyo Shibaura Denki Kabushiki Kaisha
InventorTetsuya Iizuka
Life of this patent
Estimating the term…
Abstract
A negative resistance device utilizing a substrate bias effect is comprised of two MOS transistors of n-channel type and p-channel type. The two transistors are connected at the sources and the gates. The drain of the n-channel MOS transistor is connected to the substrate of the p-channel MOS transistor. The drain of the p-channel MOS transistor is connected to the substrate of the n-channel MOS transistor.
Claims8
A negative resistance device comprising:
- a semiconductor substrate of a first conductivity type;
- a first IGFET of a first channel type formed in the semiconductor substrate, the first IGFET having a drain terminal, a source terminal, a gate terminal, a substrate terminal, a drain region, a source region and a channel region;
- and
- a second IGFET of a second channel type formed in the semiconductor substrate, the second IGFET having a drain terminal, a source terminal, a gate terminal, a substrate terminal, a drain region, a source region and a channel region;
- both the source terminal and gate terminal of said first IGFET being connected to the source and gate terminals of said second IGFET, the drain terminal of said first IGFET being connected to the substrate terminal of said second IGFET, the drain terminal of said second IGFET being connected to the substrate terminal of said first IGFET, and the drain regions and the channel regions of said first and second IGFETs being formed below a common gate electrode layer and overlapping the common gate electrode layer;
- and
- said first and second IGFETs comprising a first region of a second conductivity type formed in the semiconductor substrate, a second region of the second conductivity type formed in the semiconductor substrate and in contact with the boundary between the semiconductor substrate and the first region, a third region of the first conductivity type formed in the first region and in contact with said boundary, a fourth region of the second conductivity type formed in the semiconductor substrate and disposed in contact with the second region and separated from said boundary, a fifth region of the first conductivity type formed in the first region and disposed in contact with the third region and separated from said boundary, an insulation layer formed on the surface of the second and third regions, and a common gate electrode layer formed on the insulation layer and overlapping the second and third regions.
4 more elements
A semiconductor device comprising a negative resistance device and a load resistor connected to the negative resistance device, said negative resistance device comprising:
- a semiconductor substrate of a first conductivity type;
- a first IGFET of a first channel type formed in the semiconductor substrate, the first IGFET having a drain terminal, a source terminal, a gate terminal, a substrate terminal, a drain region, a source region and a channel region;
- and
- a second IGFET of a second channel type formed in the semiconductor substrate, the second IGFET having a drain terminal, a source terminal, a gate terminal, a substrate terminal, a drain region, a source region and a channel region;
- both the source terminal and gate terminal of said first IGFET being connected to the source and gate terminals of said second IGFET, the drain terminal of said first IGFET being connected to the substrate terminal of said second IGFET, the drain terminal of said second IGFET being connected to the substrate terminal of said first IGFET, and the drain regions and channel regions of said first and second IGFETs being formed below a common gate electrode layer and overlapping the common gate electrode layer;
- and
- said first and second IGFETs comprising a first region of a second conductivity type formed in the semiconductor substrate, a second region of the second conductivity type formed in the semiconductor substrate and in contact with the boundary between the semiconductor substrate and the first region, a third region of the first conductivity type formed in the first region and in contact with said boundary, a fourth region of the second conductivity type formed in the semiconductor substrate and disposed in contact with the second region and separated from said boundary, a fifth region of the first conductivity type formed in the first region and disposed in contact with the third region and separated from said boundary, an insulation layer formed on the surface of the second and third regions, and a common gate electrode layer formed on the insulating layer and overlapping the second and third regions.
4 more elements
Dependencies are inferred from the claim text.