Charge transfer memory in serial-parallel-serial organization

In a series-parallel-series charge transfer memory integrated on a chip for four phase operation, in which series read-in and read-out chains each comprise charge transfer elements each having a memory electrode and a transfer electrode, in which corresponding electrodes of each second charge transfer element of the read-in chain and of the read-out chain has coupled thereto a group of at least two of the parallel chains, and in which the four clock pulse voltages for the read-in chain and the read-out chain are supplied via respective clock lines, the improvement wherein:

• the electrodes associated with a respective clock pulse voltage comprise a continuous polysilicon strip conductor;
• that the transfer electrodes comprise comb-shaped structures;
• and
• the four polysilicon conductors are arranged with respect to the transfer electrodes such that a tooth of the comb shaped structure assigned to a memory electrode is partially covered by two teeth belonging to different transfer electrodes on opposite sides thereof so that the required clock pulse voltages are fed to the electrodes directly by way of the polysilicon conductors.