US 4,380,113 AGranted

Process for fabricating a high capacity memory cell

AssigneeSignetics Corporation

InventorManohar L. Malwah

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Abstract

A method of fabricating an array of high capacity memory cells comprises patterning a semiconductor surface to form memory cell areas; covering the memory cell areas with insulator; forming an ion layer of first conductivity type throughout the insulator; forming an ion layer of second conductivity type throughout the semiconductor surface; forming a first conductive pattern over the insulating layer to form a storage gate and to define a storage region extending to an isolation region and to define a transfer region spaced from the isolation region by the storage region; removing ions of first conductivity type from the portion of insulator above the transfer region and from other active areas; removing ions of second conductivity type from the transfer region and other active areas; diffusing ions of first conductivity type from the insulating layer to the storage region to produce in the storage region a shallow ion layer of first conductivity type and a deep ion layer of second conductivity type; and forming a second conductivity pattern over the transfer region to define a bit line region spaced from the storage region by a portion of the transfer region and to produce a transfer gate overlying the transfer region portion and also insulated from and partially overlying the storage gate.

Claims9

Dependent claims

A method of fabricating a high capacity memory cell, comprising:

(a) forming isolation regions in a surface of a semiconductor substrate patterned to produce a multiplicity of cell areas;
(b) forming an insulating layer over the entire surface of said cell areas;
(c) introducing ions having majority carriers of first conductivity type throughout the entire area of said insulating layer;
(d) introducing ions having majority carriers of second conductivity type opposite said first conductivity type throughout the entire area of the semiconductor surface.
(e) forming a first pattern of conductive material over said insulating layer to form a storage gate and to define a storage region beneath said storage gate extending to an isolation region and to define a transfer region spaced from said isolation region by said storage region;
(f) removing said insulating layer from the portion lying above said transfer region and from other active areas to selectively remove ions having majority carriers of said first conductivity type;
(g) removing ions having majority carriers of said second conductivity type from said transfer region and other active areas by forming an oxide layer on the semiconductor surface where said insulating layer is removed;
(h) diffusing ions having majority carriers of said first conductivity type from said insulating layer to said storage region to produce in said storage region a shallow ion layer having majority carriers of said first conductivity type and beneath said shallow ion layer a deep ion layer having majority carriers of said second conductivity type;
and
(i) forming a second pattern of conductive material over said transfer region to define a bit line region spaced from said storage region by a portion of said transfer region and to produce a transfer gate overlying said transfer region portion and also insulated from and partially overlying said storage gate.

7 more elements

Dependencies are inferred from the claim text.