High density dynamic memory cell
AssigneeTexas Instruments Incorporated
InventorsShyh-Chang Tsaur, Chang-Kiang Kuo
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Abstract
A dynamic read/write memory cell of the one transistor N-channel silicon gate type is made by a triple-level polysilicon process which allows the bit lines to be formed by metal strips which have low resistance and which can cover the storage capacitors for alpha particle protection. Metal-to-silicon contacts are made through an intervening polysilicon segment which allows the underlying N+ silicon region to be much smaller than in prior cells. The polysilicon segment also prevents the occurance of problems with spiking of metal through shallow implanted N+ regions.
Claims15
A semiconductor memory device including an array of rows and columns of one-transistor dynamic memory cells in a face of a semiconductor body, each cell having a capacitor and having an access transistor with a source-to-drain path and a gate, the memory device comprising:
- a plurality of semiconductor regions in said face of the semiconductor body, said regions being laterally spaced from one another along said face, each region providing one end of the source-to-drain path of two of the access transistors for two adjacent cells in a column,
- a plurality of electrodes at said face adjacent said regions, each electrode providing the gate of an access transistor,
- a plurality of connector areas of said face arranged in columns, each of the areas being for the purpose of making electrical connection separately to one of said regions to thereby provide a connection to two adjacent cells,
- conductive means extending laterally along said face partially underlying said plurality of electrodes but insulated therefrom by an insulating layer, the conductive means providing a common plate for all of the capacitors of all of the cells, and
- a plurality of strips of conductive material extending along said face but insulated therefrom, each of the strips making electrical connection to a plurality of said connector areas thereby providing column lines.
A semiconductor memory device including an array of rows and columns of one-transistor dynamic memory cells in a face of a semiconductor body, each cell having a capacitor and having an access transistor of the insulated gate field-effect type with a source-to-drain path and a gate, the memory device comprising:
- a plurality of semiconductor regions in said face of the semiconductor body, said regions being laterally spaced from one another along said face with thick field oxide in said face between the regions, each region providing one end of the source-to-drain path of the two access transistors for two adjacent cells in a column,
- a plurality of electrodes at said face adjacent said regions, each electrode providing the gate of an access transistor,
- a plurality of connector areas at said face arranged in columns, each of the areas being for the purpose of making electrical connection separately to one of said regions to thereby provide a connection to two adjacent cells,
- conductive means extending laterally along said face insulated from said electrodes, the conductive means providing an upper plate for all of the capacitors of all of the cells and overlying a capacitor area for each individual cell, the capacitor areas in each of said pairs of adjacent cells having separated on said face from other pairs but not from one another by said thick field oxide, and
- a plurality of parallel strips of conductive material extending along said face but insulated therefrom, each of the strips making electrical connection to a plurality of said connector areas and thereby providing column lines.
A semiconductor memory device including an array of rows and columns of one-transistor dynamic memory cells in a face of a semiconductor body, each cell having a capacitor and having an access transistor of the insulated gate field-effect type with a source-to-drain path and a gate, the memory device comprising:
- a plurality of semiconductor regions in said face of the semiconductor body, said regions being laterally separated from one another along said face by thick field oxide recessed in said face between the regions, each region having a pair of said cells therein and including a common N+ area of the face as one end of the source-to-drain path of the two access transistors for two adjacent cells in a column,
- a plurality of gate electrodes at said face over parts of said regions, each providing the gate of one of the access transistors,
- a plurality of elongated conductive strips providing column lines, the column lines including connector areas at said face, each of the areas being for the purpose of making electrical connection separately to one of said common N+ areas to thereby provide a connection to two adjacent cells of a column,
- conductive means extending laterally along said face insulated from said electrodes, the conductive means providing an upper plate for the capacitors of all of the cells and overlying a capacitor area of the semiconductor region for each individual cell,
- the two capacitor areas in each of said semiconductor regions being at opposite ends of the region and wider than said common N+ area, the two capacitor areas being separated on said face from other semiconductor regions but not from one another by said thick field oxide.
Dependencies are inferred from the claim text.