Power static induction transistor fabrication

A method for forming a gate-source structure for a recessed-gate static induction transistor, said method comprising the steps of:

• growing a high resistivity epitaxial silicon layer on a semiconductor substrate;
• growing a silicon dioxide layer over said epitaxial layer;
• etching parallel windows through said silicon dioxide layer at predetermined gate and source locations;
• masking said source windows and etching recessed gate grooves in said epitaxial layer, said gate grooves having depth substantially greater than width;
• removing said source window masking;
• depositing a doped polysilicon layer in said gate grooves, in said source windows and on said silicon dioxide layer, said deposit continuing until the surface of said polysilicon layer is substantially planar;
• removing said doped polysilicon layer to open said source windows and to form gate contact regions, said doped layer removal accomplished using relaxed registration photolithography;
• forming source regions in said epitaxial layer at source window locations;
• and
• depositing metal in said source window and over said gate contact regions to form gate and source electrodes, said metal depositing accomplished using relaxed registration photolithography.