CMOS Frequency divider circuit having invalid signal override

In a timing system having means for providing an input signal at a primary frequency, a frequency divider circuit for providing an output signal at a secondary frequency one-third that of the primary frequency, the divider circuit comprising:

• a first divider stage including first storage means for maintaining a logical condition therein, first logic means for establishing a logical high condition in said first storage means in response to a logical low input signal when a third storage means is in the logical low condition and for leaving said logical condition in said first storage means unchanged otherwise, and second logic means for establishing a logical low condition in said first storage means in response to a logical high input signal when said third storage means is in a logical high condition and for leaving said logical state in said first storage means unchanged otherwise;
• second divider stage including second storage means for maintaining a logical condition therein, third logic means for establishing a logical high condition in said second storage means in response to a logical low input signal when said first storage means is in the logical low condition and for leaving said logical condition of said second storage means unchanged otherwise, and fourth logic means for establishing a logical low condition in said second storage means in response to a logical high input signal when said first storage means is in the logical high condition and for leaving said logical condition in said second storage means unchanged otherwise;
• third divider stage including said third storage means for maintaining a logical condition therein, fifth logic means for establishing a logical high condition in said third storage means in response to a logical low input signal when said second storage means is in the logical low condition and for leaving said logical condition of said third storage means unchanged otherwise, and sixth logic means for establishing a logical low condition in said third storage means in response to a logical high input signal when said second storage means is in the logical high condition and for leaving said logical condition in said third storage means unchanged otherwise;
• and
• override means including means for detecting the logical condition of said first and second storage means and means for establishing the opposite logical condition in said third storage means in response to detecting the same logical condition on both said first and second storage means.