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US 4,366,559 AGranted
Memory device
AssigneeNippon Electric Co., Ltd.
InventorsTetsuo Misaizu, Masumi Nakao
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AssigneeNippon Electric Co., Ltd.
InventorsTetsuo Misaizu, Masumi Nakao
Estimating the term…
A memory device which is stable in operation and operable at high speed is disclosed. The memory device comprises a plurality of pairs of digit lines, a plurality of sense amplifiers having a pair of input terminals, a plurality of pairs of gating means and a plurality of memory cells and is characterized in that the pair of input terminals of the sense amplifiers are operatively coupled through the pair of gating means to the pair of digit lines.
A semiconductor memory device comprising a sense amplifier having a first input terminal and a second input terminal, a first digit line arranged on a first side of said sense amplifier, a second digit line arranged in parallel with and adjacent to said first digit line, a third digit line arranged on a second and opposite side of said sense amplifier, a fourth digit line arranged in parallel with and adjacent to said third digit line, a first group of memory cells coupled to said first digit line, a second group of memory cells coupled to said second digit line, a third group of memory cells coupled to said third digit line, a fourth group of memory cells coupled to said fourth digit line, a first means for selectively connecting said first digit line to said first input terminal, second means for selectively connecting said second digit line to said first input terminal, third means for selectively connecting said third digit line to said second input terminal, fourth means for selectively connecting said fourth digit line to said second input terminal, first control means for enabling one of said first and second means to connect a selected one of said first and second digit lines to said first input terminal and second control means for enabling one of said third and fourth means to connect a selected one of said third and fourth digit lines to said second input terminal.
A semiconductor memory device comprising a sense amplifier having a first input terminal and a second input terminal, a first digit line arranged on a first side of said sense amplifier, a first group of memory cells coupled to said first digit line, a second digit line arranged on a second side of said sense amplifier, a second group of memory cells coupled to said second digit line, said first side and said second side having a symmetrical relation with respect to said sense amplifier, a third digit line arranged on said first side in parallel with and adjacent to said first digit line, a third group of memory cells coupled to said third digit line, a fourth digit line arranged on said second side in parallel with and adjacent to said second digit line, a fourth group of memory cells coupled to said fourth digit line, first means for selectively connecting said first digit line to said first input terminal, second means for selectively connecting said second digit line to second input terminal, third means for selectively connecting said third digit line to said first input terminal, fourth means for selectively connecting said fourth digit line to said second input terminal, a first control line coupled to said first and third means in common, a second control line coupled to said second and fourth means, and control means for selectively energizing one of said first and second control lines.
A semiconductor memory device comprising a sense amplifier having a first input terminal and a second input terminal, a first digit line arranged on a first side of said sense amplifier, a second digit line arranged on said first side and in parallel to said first digit line, a third digit line arranged on a second and opposite side of said sense amplifier, a fourth digit line arranged on said second side and in parallel to said third digit line, a first group of memory cells coupled to said first digit line, a second group of memory cells coupled to said second digit line, a third group of memory cells coupled to said third digit line, a fourth group of memory cells coupled to said fourth digit line, a first switching gate coupled between said first digit line and said first input terminal and arranged on said first side, a second switching gate coupled between said second digit line and said second input terminal and arranged on said first side, a third switching gate coupled between said third digit line and said first input terminal and arranged on said second side, a fourth switching gate coupled between said fourth digit line and said second input terminal and arranged on said second side, a first control line at least on said first side, said first control line having electrical connection to said first and second switching gates, a second control line at least on said second side, said second control line having electrical connection to said third and fourth switching gates, and means responsive to address information for selectively supplying one of said first and second control lines with a selection signal.
A memory device comprising a plurality of sense amplifiers arranged in row direction, each of said sense amplifiers having a pair of input terminals, a plurality of first digit line pairs, each of said first digit line pairs being arranged on a first side of associated one of said sense amplifiers and in a column direction, a plurality of second digit line pairs, each of said second digit line pairs being arranged on a second side of associated one of said sense amplifiers and in the column direction, a plurality of memory cells coupled to the respective digit lines, a plurality of first transfer gate pairs arranged in a first row adjacent to a first side of the row of said sense amplifiers, each of said first transfer gate pairs operatively connecting each of said first digit line pairs to the pair of input terminals of associated one of said sense amplifiers, a plurality of second transfer gate pairs arranged in a second side of said row of said sense amplifiers opposite to said first side with respect to said sense amplifiers, each of said second transfer gate pairs operatively connecting each of said second digit line pairs to the pair of input terminals of associated one of said sense amplifiers, a first control line arranged along the rows of said first transfer gate pairs, said first control line having electrical connection to said first transfer gate pairs, a second control line arranged along the rows of said second transfer gate pairs and electrically connected to said second transfer gates, and means selectively energizing one of said first and second control lines, whereby said plurality of sense amplifiers are utilized for either of said first and second digit line pairs.
A semiconductor memory device comprising a sense amplifier having a first input terminal and a second input terminal, a first digit line arranged on a first side of said sense amplifier, a second digit line arranged in parallel and adjacent to said first digit line, a third digit line arranged on a second and opposite side of said sense amplifier, a fourth digit line arranged in parallel and adjacent to said third digit line, a plurality of memory cells coupled to said digit lines, a first transfer gate arranged between said first digit line and said sense amplifier, a second transfer gate arranged between said second digit line and said sense amplifier, a third transfer gate arranged between said third digit line and sense amplifier, a fourth transfer gate arranged between said fourth digit line and said sense amplifier, means for receiving address signal, and means responsive to said address signal for enabling two of said first to fourth transfer gates thereby to electrically connect two of said first to fourth digit lines to said first and second input terminals of said sense amplifier.
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
From the US filing history. Foreign family members aren’t listed.
Dynamic random access memory [dram] devices
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with one charge-transfer gate, e.g. MOS transistor, per cell
Read-write [R-W] circuits: bit-line organisation, e.g. bit-line layout, folded bit lines
Electronic memory devices
Term ended 28 Dec 1999 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
The present invention relates to a memory device, and more particularly to a semiconductor memory device which is fabricated as a semiconductor integrated circuit.
Semiconductor memory devices have come to have large memory capacities, and the internal signals read-out signals from memory cells are reduced to a minute level. For stably processing the reduced read-out signals and for realizing high-speed operations, a construction of a memory device in which a signal emitted from a memory cell onto a digit line is once amplified by means of a differential amplifier called a "digit sense amplifier" and then transmitted to an external device, is often used. In such memory devices, those employing one-transistor type memory cells having one transistor and one capacitor are generally utilized. Such a memory device is constructed by disposing a memory cell at every cross-point of a matrix formed by a plurality of word lines and a plurality of digit lines each coupled to a sense amplifier. The sense amplifier is provided with a signal read-out from a memory cell via a digit line and amplifies the signal. In recent years, memory capacity has been enlarged and the number of memory cells connected to one digit line has been greatly increased. Consequently, an electrostatic capacitance of the digit line has been inevitably increased. Therefore, a level of an input signal to a sense amplifier is often reduced, resulting in malfunctions of the sense amplifier. For the purpose of compensating for such reduction of the input signal level, it has been necessary to make a sense amplifier highly senstitive and/or to increase an electrostatic capacitance of memory cells themselves for enhancing the level read-out from a selected cell on the digit line. As a result there has been a disadvantage that a chip size is eventually enlarged. In addition, increase in an electrostatic capacitance formed by a digit line in itself results in a delay circuit having a large time-constant, and hence the prior art device also has a disadvantage that a speed of read-out operations is greatly reduced.
Moreover, prior to respective read-out operation, it is necessary to charge digit line up to a predetermined potential to effect the so-called precharge. When a sense amplifier operates to amplify the read-out signal, among the precharged digit lines one having a lower readout signal applied thereto will be discharged to the ground potential. Accordingly, increase in the digit line capacitance would disadvantageously result in increase in dynamic power consumption.
Other features and advantages of the present invention will become apparent upon a perusal of the following specification taken in connection with the accompanying drawings wherein:
FIG. 1 is a circuit diagram showing an one-transistor memory cell,
FIG. 2 is a circuit diagram showing a reference cell,
Referring now to FIG. 1 of the drawings, a memory cell of one-transistor type is illustrated, in which one end of a capacitor element C for holding logical information as a potential is coupled to a terminal T to which a constant potential is applied, and the other end of the capacitive element C is coupled via a source-drain path of a switching MOS transistor Q to a digit line D. Read-out and write-in of logical information is effected between the capacitor element C and the digit line D through this transistor Q. To the gate of the transistor Q is connected a word line A.
FIG. 2 shows a reference cell for applying a reference potential to a digit sense amplifier. A capacitive element Cr of a reference cell has a smaller capacitance than that of the capacitive element C of the memory cell, in which one end of the capacitor Cr is coupled to a fixed potential terminal T and the other end is connected to both a reset transistor Qr and the switching transistor Q. The other end of the transistor Q is coupled to a digit line and the gate of the transistor Q is coupled to a reference word line AR. The other end of Qr and the gate of Qr are grounded and coupled to a terminal R, respectively.
With regard to a structure of a memory cell, for instance, as shown in FIGS. 3 and 4, an N-type diffusion layer 12 as a drain of a switching transistor is formed in a P-type semiconductor substrate 11, and the diffusion layer 12 is connected via a contact portion 13 to a metallic wiring layer D as a digit line. Adjacent to the diffusion layer 12, within an insulator layer 14 is formed an address line A of a polycrystalline silicon layer. Adjacent to this word line A, within the same insulator layer 14 is formed one electrode 15 of a capacitor element C in a memory cell, which electrode consists of a polycrystalline silicon layer.