I.sup.2 L Memory device

A semiconductor memory device comprising a first transistor (TR1) of a first conductivity type, a second transistor (TR2) of the first conductivity type having its emitter, collector and base connected to the emitter, base and collector of the first transistor (TR1), a third transistor (TR5) of a second conductivity type opposite to said first conductivity type which has its base and collector connected to the emitter and base of the second transistor (TR2), and first and second impedance elements (TR3, TR4) having their first ends connected to the collectors of the first and second transistors (TR1, TR2) and their second ends connected to each other;

• and further including a fourth transistor (TR6, TR8) of the first conductivity type having its base and emitter connected to the collector and emitter of one of the first and second transistors (TR1, TR2) and a third impedance element has its one end connected to the base of the fourth transistor (TR6, TR8), wherein said first and second impedance elements (TR3, TR4) are comprised of sixth and seventh transistors of the second conductivity type having their emitter connected to each other, their bases connected to each other and their collectors connected to the collectors of said first and second transistors (TR1, TR2), said third impedance element (TR7) is constituted of an eighth transistor of the second conductivity type having its base and collector connected to the emitter and base of said third transistor (TR6), said sixth transistor (TR3) and second transistor (TR2) constitute a first IIL logic gate circuit, said seventh transistor (TR4) and first transistor (TR1) constitute a second IIL logic gate circuit and said eighth transistor (TR7) and fourth transistor (TR6) constitute a third IIL logic gate circuit.

A semiconductor memory device comprising a first transistor (TR1) of a first conductivity type, a second transistor (TR2) of the first conductivity type having its emitter, collector and base respectively connected to the emitter, base and collector of the first transistor (TR1), a third transistor (TR5) of a second conductivity type opposite to said first conductivity type which has its base and collector respectively connected to the emitter and base of the second transistor (TR2), memory cells arranged in a matrix array and each constituted of first and second impedance elements (TR3, TR4) having their first ends connected to the collectors of the first and second transistors and their second ends connected to each other, a first data line (DL) commonly connected to the emitter of the third transistor (TR5) of the memory cell on the same column and a first row select line (WL) commonly connected to the second ends of the first and second impedances (TR3, TR4) of the memory cell on the same row, in which each of said memory cells comprises a fourth transistor (TR6 or TR8) of the first conductivity type having its base and emitter respectively connected to the collector and emitter of one of said first and second transistors (TR1, TR2) and a third impedance element (TR7) having one end connected to the base of the fourth transistor (TR6 or TR8) and the other end connected to a second row select line.

A semiconductor memory device comprising a first transistor (TR1) of a first conductivity type, a second transistor (TR2) of the first conductivity type having its emitter, collector and base connected to the emitter, base and collector of the first transistor (TR1), a third transistor (TR5) of a second conductivity type opposite to said first conductivity type which has its base and collector connected to the emitter and base of the second transistor (TR2), memory cells arranged in a matrix array and constituted of first and second impedance elements (TR3, TR4) having their first ends connected to the collectors of the first and second transistors and their second ends connected to each other, a first data line (DL) commonly connected to the emitter of the third transistor (TR5) of the memory cell on the same column and a first row select line (WL) commonly connected to the second ends of the first and second impedances (TR3, TR4) of the memory cell on the same row, in which each of said memory cells comprises a fourth transistor (TR6, TR8) of the first conductivity type having its base and emitter connected to the collector and emitter of one of said first and second transistor (TR1, TR2) and its collector connected to the base of said second transistor (TR2) and a third impedance element having its end connected to the base of the fourth transistor (TR6, TR8) and its other end connected to a second row select line.

A semiconductor memory device comprising a first transistor (TR1) of a first conductivity type, a second transisor (TR2) of the first conductivity type having its emitter, collector and base connected to the emitter, base and collector of the first transistor (TR1), a third transistor (TR5) of a second conductivity type opposite to said first conductivity type which has its base and collector connected to the emitter and base of the second transistor (TR2), memory cells arranged in a matrix array and constituted of first and second impedance elements (TR3, TR4) having their first ends connected to the collectors of the first and second transistors and their second ends connected to each other, a first data line (DL) commonly connected to the emitter of the third transistor (TR5) of the memory cell on the same column and a first row select line (WL) commonly connected to the second ends of the first and second impedances (TR3, TR4) of the memory cell on the same row, in which each of said memory cells comprises a fourth transistor (TR6, TR8) of the first conductivity type having its base and emitter connected to the collector and emitter of one of said first and second transistors (TR1, TR2), a third impedance element having its end connected to the base of the fourth transistor (TR6, TR8) and its other end connected to a second row select line and a fifth transistor (TR9) of the first conductivity type having its collector-emitter path connected between the base and emitter of said second transistor (TR2).

A semiconductor memory device comprising a first transistor (TR1) of a first conductivity type, a second transistor (TR2) of the first conductivity type having its emitter, collector and base connected to the emitter, base and collector of the first transistor (TR1), a third transistor (TR5) of a second conductivity type opposite to said first conductivity type which has its base and collector connected to the emitter and base of the second transistor (TR2), memory cells arranged in a matrix array and constituted of first and second impedance elements (TR3, TR4) having their first ends connected to the collectors of the first and second transistors and their second ends connected to each other, a first data line (DL) commonly connected to the emitter of the third transistor (TR5) of the memory cell on the same column and a first row select line (WL) commonly connected to the second ends of the first and second impedances (TR3), TR4) of the memory cell on the same row, in which each of said memory cells comprises a fourth transistor (TR6, TR8) of the first conductivity type having its base and emitter connected to the collector and emitter of one of said first and second transistors (TR1, TR2) and a third impedance element having its end connected to the base of the fourth transistor (TR6, TR8) and its other end connected to a second row select line, wherein said first and second impedance elements (TR3, TR4) are constituted of sixth and seventh transistors of the second conductivity type having their emitters connected to each other, their bases connected to each other and their collectors connected to the collectors of the first and second transistors (TR1, TR2), said third impedance (TR7) is constituted of an eight transistor of the second conductivity type having its base and collector connected to the emitter and base of said fourth transistor (TR6,), said sixth transistor (TR3) and second transistor (TR2) constitute a first IIL logic gate circuit, said seventh transistor (TR4) and first transistor (TR1) constitute a second ILL logic gate circuit, and said transistor (TR7) and fourth transistor (TR6) constitute a third IIL logic gate circuit.