Vertical MOSFET with reduced turn-on resistance

A VDMOS device comprising a semiconductor wafer having first and second major planar surfaces, and including therein:

• a source region of a first conductivity type adjacent to a body region of a second conductivity type, both regions intercepting the first major surface,
• a high conductivity drain region of the first conductivity type, intercepting the second major surface, and
• an extended drain region of the first conductivity type adjacently disposed between the high conductivity drain and body regions, and intercepting the first major surface so as to define a channel region in an area of the body region at the first surface, said extended drain region being of lower conductivity than the high conductivity drain region and providing substantially uniform spacing between the body and high conductivity drain regions, the high conductivity drain region comprising a projection extending toward the first surface in an area where the extended drain intercepts the first surface.