Divide by three clock divider with symmetrical output
AssigneeRockwell International Corporation
InventorsSteven J. Clendening, Tello D. Adams
Life of this patent
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Abstract
A flip-flop receives clock pulses of frequency F and is alternately set and reset on alternate inverted third clock pulse edges by logic responsive to the clock pulses and to the output of the flip-flop. The logic includes a second flip-flop and a pair of gates which maintain the set and reset states of the first flip-flop for two consecutive clock pulse edges between set and reset transitions to provide symmetrical output pulses from the first flip-flop of frequency 1/3F with a substantially 50% duty cycle.
Claims9
A divide by three digital clock divider circuit providing a symmetrical output, comprising:
- flip-flop means for receiving clock pulses of frequency F;
- and
- second means for alternately setting and resetting said flip-flop means on alternate inverted third clock pulse edges, and for maintaining the set and reset states of said flip-flop means for two consecutive clock pulse edges between set and reset transitions on said alternate third inverted clock pulse edges to provide symmetrical output pulses of frequency 1/3F with a substantially 50% duty cycle,
- said second means comprising logic means responsive directly to said clock pulses and to the output of said first flip-flop means for resetting said first flip-flop means every sixth clock pulse edge and for setting said first flip-flop means every third clock pulse edge following a reset clock pulse edge such that said flip-flop means is set every sixth clock pulse edge symmetrically interleaved with said resetting.
A divide by three digital clock divider circuit providing a symmetrical output, comprising:
- first flip-flop means for receiving clock pulses of frequency F;
- and
- second means for alternately setting and resetting said flip-flop means on alternate inverted third clock pulse edges, and for maintaining the set and reset states of said flip-flop means for two consecutive clock pulse edges between set and reset transitions on said alternate third inverted clock pulse edges to provide symmetrical output pulses of frequency 1/3F with a substantially 50% duty cycle,
- said second means comprising logic means responsive to said clock pulses and to the output of said first flip-flop means for resetting said first flip-flop means every sixth clock pulse edge and for setting said first flip-flop means every third clock pulse edge following a reset clock pulse edge such that said flip-flop means is set every sixth clock pulse edge symmetrically interleaved with said resetting wherein,
- second flip-flop means receives said clock pulses and the output of said first mentioned flip-flop means, and
- gate means receives said clock pulses and the output of said second flip-flop means, and outputs a reset signal to a reset input of said first flip-flop means, and outputs a set signal to a data input of said first flip-flop means for clocking therethrough by said clock pulses.
A divide by three digital clock divider circuit providing a symmetrical output, comprising:
- a pair of flip-flops concurrently clocked by clock pulses of frequency F, the first flip-flop having an output connected to an input of the second flip-flop;
- and
- gate means receiving said clock pulses and an output of said second flip-flop, and delivering alternate control signals to said first flip-flop at every third clock pulse edge for alternately setting and resetting said first flip-flop on alternate inverted third clock pulse edges such that said output of said first flip-flop provides symmetrical pulses of frequency 1/3F with a substantially 50% duty cycle.
Dependencies are inferred from the claim text.