Semiconductor device with monitor pattern, and a method of monitoring device parameters

A monitoring method for use in a process for producing a semiconductor device comprising a chip having at least one semiconductor circuit element and a monitor pattern thereon, comprising the steps of:

• forming said monitor pattern in a predetermined area of the chip simultaneously with the formation of said at least one circuit element in the remaining area of the chip, said monitor pattern comprising:
• a semiconductor layer of a first conductivity type formed on a substrate;
• a first region of a second conductivity type formed in said semiconductor layer;
• a second region of the first conductivity type formed in said first region, said first region being superficially divided into first and second portions by said second region;
• and
• a third region of the second conductivity type formed in said semiconductor layer and electrically connected to said substrate and to said first portion of said first region, at least a part of the surface of said second portion of said first region being exposed to enable electrical contact thereto;
• and said method further comprising the steps of:
• applying a voltage between said second portion of said first region at said exposed, electrical contact surface thereof and said substrate;
• and
• measuring the pinch off resistance of said monitor pattern as an index of the current gain of the semiconductor device.

A method for producing a plurality of semiconductor devices in a wafer delineated to define a plurality of corresponding chips, each said chip comprising a semiconductor layer of a first conductivity type formed on a substrate of a second conductivity type, said layer and said substrate being common to said plural chips of said wafer, and at least certain of said chips comprise at least one semiconductor circuit element and a monitor pattern, comprising the steps of:

• defining a predetermined area of each of said certain chips for having formed therein a monitor pattern for that chip simultaneously with the formation of said at least one semiconductor circuit element on the remaining area of said chip;
• forming a first region of a second conductivity type in said semiconductor layer of each said chip,
• forming a second region of the first conductivity type in said first region, said second region dividing said first region into first and second portions,
• forming a third region of the second conductivity type in said semiconductor layer, extending to and electrically connected with said substrate and overlapping and being electrically connected to one of said first and second portions of said second region, at least a part of the surface of the other of said two portions of said first region being exposed to afford electrical contact thereto,
• applying a voltage to at least selected said chips of said wafer, during a diffusion process for forming said second region of said monitor pattern in said chips, between the other said portion of said first region at said exposed, electrical contact surface thereof and said substrate of each said selected chip to produce an electrical current flow therethrough, and
• determining the resistance to the flow of current for deriving a value of the pinch off resistance of said monitor pattern in each of said selected chips.

A wafer comprising:

• a plurality of chips, each said chip comprising a monitor pattern formed in one corner thereof and at least one semiconductor circuit element;
• a plurality of cutting lines formed in said wafer between adjacent ones of said chips;
• and
• each said monitor pattern comprises a substrate, a semiconductor layer of a first conductivity type formed on said substrate, a first region of a second conductivity type formed in said semiconductor layer, a second region of said first conductivity type formed in said first region in such position that the surface of said first region is divided into two portions by said second region, and a third region of said second conductivity type formed in said semiconductor layer and electrically connected to said substrate and to one of said two portions of said first region, at least a part of the surface of the other portion of said first region being exposed to enable electrical contact thereto.