Non-volatile EPROM with enhanced drain overlap for increased efficiency
OwnerEliyahou Harariinventor
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OwnerEliyahou Harariinventor
Estimating the term…
The floating gate in an N channel EPROM cell extends over the drain diffusion and over a portion of the channel thereby to form a "drain" capacitance between the drain and the floating gate and a "channel" capacitance between the channel and the floating gate. A control gate overlaps the floating gate and extends over the remainder of the channel near the source diffusion thereby to form a "control" capacitance between the channel and the control gate. These three capacitances form the coupling for driving each cell. The inversion region in the channel directly under the control gate is established directly by a "write or read access" voltage applied to the control gate. The inversion region in the channel directly under the floating gate is established indirectly through the drain and control capacitances and the channel capacitance by the control gate voltage and by another write access voltage applied to the drain. In effect, the drain voltage is coupled to the portion of the channel adjacent to the drain through the series driving circuit formed by the drain capacitance and the channel capacitance. During write, hot electrons from the write channel current are directed toward and injected into the floating gate by the transverse electric field between the floating gate and the underlying channel. Stored injection charge on the floating gate raises the conduction threshold of the programmed cell, causing the cell to remain non-conductive during read when standard ("low") access voltages are applied to the control gate. An unprogrammed cell conducts in response to the low read voltages applied to its control gate and drain drive circuit. A cell is erased either by ultraviolet illumination or by electrons from the floating gate tunneling through a region of thinned oxide. The non-symmetrical arrangement of the control gate and floating gate with respect to source and drain allows a very dense array implementation.
A semiconductor memory structure formed in semiconductor material of a first conductivity type with memory cells and access circuitry formed in a portion of the top surface of said semiconductor material and with those portions of this top surface in which memory cells and access circuitry are not formed comprising the field of the structure comprising:
A semiconductor memory structure comprising a plurality of memory cells and a field region surrounding each of said memory cells, wherein each memory cell comprises a source region of a first conductivity type and a drain region of said first conductivity type with a channel region of a second conductivity type opposite said first conductivity type therebetween, and wherein the field of the structure includes channel stop regions of said second conductivity type and a higher doping concentration than in said channel region formed over only a portion of said field region so as to reduce the capacitance between the memory cells and the field region.
Dependencies are inferred from the claim text.