Current hogging logic circuit with npn vertical reversal transistor and diode/pnp vertical transistor output

A logic structure of the siicon planar type comprising:

• a silicon substrate;
• lateral pnp transistor structures constituting a plurality of logic elements arranged in successive logic stages, each stage set in an n-type island portion (14) of an epitaxial layer serving as a common base element, each said pnp transistor structure comprising for each logic element:
• a p-type diffusion-formed emitter zone (E);
• a p-type diffusion-formed output collector zone (C.sub.0) in the neighborhood of said emitter zone;
• at least one additional p-type diffusion-formed control collector (C.sub.1, C.sub.2) located between said emitter zone and said output collector zone, the number and dispostion thereof being chosen for performance of a logic function with respect to every control collector current as logic input and output collector current as logic output, by virtue of the ability of each said control collector (C.sub.1, C.sub.2) positioned as aforesaid to prevent, when provided with voltage bias negative with respect to said emitter zone (E) charge carriers injected by said emitter zone (E) from reaching portions of said output collector zone (C.sub.0) screened from said emitter zone by the particular control collector zone;
• an npn output current reversal transistor (T.sub.r) coupled to said output collector zone, having a base which is constituted by a p-type zone diffusion formed in an n-type layer that is separated by a p-type isolation strip from the n-type layer in which said output collector zone is diffusion formed but which p-type base zone is electrically connected to said output collector zone (C.sub.0), said current reversal transistor having a collector which feeds the output connection for the logic output of the logic element to which said output collector zone (C.sub.0) belongs;
• connections being provided for causing the output of said element of one stage to control the respective collector zones of a plurality of said elements in following stages;
• and
• vertical pnp transistors, for purposes including addition of current amplification to the current amplification provided by said current reversal transistors of the respective logic stages, respectively connected to the collector zones of said logic elements in said following stages.

A logic structure of the silicon planar type comprising:

• a silicon substrate;
• lateral pnp transistor structures constituting at least one logic element set in an n-type island portion (14) of epitaxial layers serving as a common base element, each said pnp transistor structure comprising, for each logic element:
• a p-type diffusion-formed emitter zone (E);
• a p-type diffusion-formed output collector zone (C.sub.0) in the neighborhood of said emitter zone;
• at least one additional p-type diffusion-formed collector zone (C.sub.1, C.sub.2) located between said emitter zone and output collector zone, the number and disposition thereof being chosen for performance of a logic function with respect to every control collector current as logic input and output collector current as logic output by virtue of the ability of each said control collector zone (C.sub.1, C.sub.2) positioned as aforesaid to prevent, when provided with voltage bias negative with respect to said emitter zone (E), charge carriers injected by said emitter zone (E) from reaching portions of said output collector zone (C.sub.0) screened from said emitter zone by said particular control collector zone;
• and
• an npn output current reversal transistor (T.sub.r) coupled to said output collector zone, having a base which is constituted by a p-type zone diffusion formed in an n-type layer that is separated by a p-type isolation strip from the n-type layer in which said output collector zone is diffusion formed but which p-type base zone is electrically connected to said output collector zone (C.sub.0), said current reversal transistor (T.sub.r) having also a collector usable for feeding an output therefrom and
• a plurality of vertical pnp transistors for providing a fanned-out output to a plurality of output connections of said logic element, the n-type base layer of each of said pnp transistors being a portion of the same semiconducting n-type layer that provides the collector of said npn output current reversal transistor and thereby providing the electric connection between said last-mentioned collector and said vertical pnp transistors.

A logic structure of the planar type comprising:

• a silicon substrate;
• lateral pnp transistor structures constituting at least one logic element set in an n-type island portion (14) of an epitaxial layer serving as a common base element, each said pnp transistor structure comprising, for each logic element:
• a p-type diffusion-formed emitter zone (E);
• a p-type diffusion-formed output collector zone (C.sub.0) in the neighborhood of said emitter zone;
• at least one additional p-type diffusion-formed collector zone (C.sub.1, C.sub.2) located between said emitter zone and said output collector zone, the number and disposition thereof being chosen for performance of a logic function with respect to every control collector current as logic input and output collector current as logic output by virtue of the ability of each said control collector zone (C.sub.1, C.sub.2) positioned as aforesaid to prevent, when provided with voltage bias negative with respect to said emitter zone (E), charge carriers injected by said said emitter zone (E) from reaching portions of said output collector zone (C.sub.0) screened from said emitter zone by said particular control collector zone;
• an npn output current reversal transistor (T.sub.r) coupled to said output collector zone, having a base which is constituted by a p-type zone diffusion formed in an n-type layer that is separated by a p-type isolation strip from the n-type layer in which said output collector zone is diffusion formed but which p-type base zone is electrically connected to said output collector zone (C.sub.0), said current reversal transistor having also a collector usable for feeding an output therefrom;
• a vertical pnp decoupling transistor for providing an output connection of said logic element, of which decoupling transistor the n-type base layer is a portion of the same semi-conducting n-type base layer that provides the collector electrode of said npn output current reversal transistor and constitutes an epitaxial island above a p-type substrate layer surrounded by said p-type isolation strip;
• said p-type isolation strip extending down to said p-type substrate;
• and
• a p-type surface strip shallower than said semi-conducting n-type layer and crossing said epitaxial island between the portion of said n-type island in which said npn current reversal transistor is located and the portion of said n-type island in which said vertical pnp decoupling transistor is located for prevention of undesired thyristor effects, said surface strip connecting at its ends with said p-type isolation strip.