Nonvolatile semiconductor memory device and method of its manufacture
AssigneeRCA Corporation
InventorsJames E. Carnes, Murray H. Woods
Life of this patent
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Abstract
An MNOS nonvolatile semiconductive memory device of the type which has a thick gate insulating layer overlapping the source and drain regions and a thin gate insulator layer in the memory portion of the device includes a region of relatively high concentration of impurities of the same type conductivity as the substrate in the portion of the channel which is beneath the thin gate insulating layer. This increases the values of both the low threshold and the high threshold states of the memory portion of the device so as to increase the threshold voltage window of the device.
Claims8
An improved nonvolatile semiconductive memory device formed in a body of semiconductor material of N type conductivity having a surface with spaced source and drain regions of P type conductivity in said body adjacent to said surface and defining the ends of a channel region of controllable conductivity, a first insulating layer on said surface over said channel region, said first insulating layer having a thin, charge tunneling portion over part of said channel region and a thick non-tunneling portion over the rest of the said channel region, a second insulating layer on said first insulating layer, and a gate electrode layer on said second insulating layer, wherein the improvement comprises:
- at least a portion of said channel region beneath said thin portion of said first insulating layer having a concentration of conductivity modifiers of said N type greater than the concentration of conductivity modifiers in the portion of said channel region beneath said thick portion of said first insulating layer.
A method of making an improved nonvolatile semiconductive memory device formed in a body of semiconductor material of one type conductivity having a surface with spaced source and drain regions of opposite type conductivity in said body adjacent to said surface and defining the ends of a channel region of controllable conductivity, a first insulating layer on said surface over said channel region, said first insulating layer having a thin, charge tunneling portion over part of said channel region and a thick non-tunneling portion over the rest of the said channel region, a second insulating layer on said first insulating layer and a gate electrode layer on said second insulating layer, comprising the step of:
- introducing conductivity modifiers into said portion of said channel region beneath said thin portion of said first insulating layer to increase the concentration thereof in said portion of said channel region to a value higher than the concentration of conductivity modifiers in the portion of said channel region beneath said thick portion of said first insulating layer.
Dependencies are inferred from the claim text.