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US 4,305,083 AGranted
Single junction charge injector floating gate memory cell
AssigneeTexas Instruments Incorporated
InventorJean M. Gutierrez
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AssigneeTexas Instruments Incorporated
InventorJean M. Gutierrez
Estimating the term…
A single charge injector, floating gate memory cell wherein the injector diode is defined by an ion implanted region of opposite conductivity type from that of the semiconductor substrate and by a diffused region having the same conductivity type as but higher conductivity than the substrate. Equal hole and electron injection efficiencies can be obtained from this single charge injector. A three terminal access cell having a compact structure is obtained by use of a thick oxide read transistor located between the injector diode and the bootstrap capacitor. The read transistor together with a single address transistor for the cell are connected to the injector diode.
A semiconductor memory cell including a semiconductor substrate of one conductivity type, an electrically isolated floating gate conductor overlying said substrate, combined hole and electron injector means defined by a single pn junction located in said substrate under said floating gate for selective operation in avalanche breakdown for alternatively injecting electrons or holes onto said gate, and control means for selectively applying operating voltages across said single injector means and to said floating gate for operating said injector means in an electron injector mode or in a hole injector mode, wherein said single injector pn junction is an abrupt junction defined by a first region having an opposite conductivity from that of the substrate and a second region having the same conductivity type as but greater impurity concentration than that of said substrate, the abrupt junction defined by regions having impurity concentrations differing from each other to the extent that said injector junction has substantially the same injection efficiency when operated in said hole injection mode or in said electron injection mode.
A semiconductor memory cell including a monocrystalline semiconductor substrate of one conductivity type, an electrically isolated floating gate conductor overlying said substrate, a combined hole and electron injector means having a single junction means defined by semiconductor regions of opposite conductivity types occupying laterally extending regions of said substrate beneath said floating gate conductor and defining between them a single pn junction means extending into the substrate transversely of the floating gate conductor for selective operation in avalanche breakdown for alternatively injecting holes or electrons onto said gate, and means for selective operation of said single junction means in a hole injection mode or in an electron injection mode including means connected to said semiconductor regions for applying a voltage across said region to bias said single junction at least to avalanche breakdown threshold and means for selectively capacitively coupling a bias voltage to said floating gate, wherein the single injector pn junction means is an abrupt junction defined between a first region doped by ion implantation to have an opposite conductivity type from that of said substrate and a second region doped by thermal diffusion to have the same conductivity type as but greater impurity concentration than that of said substrate, the impurity concentrations of the first and second regions defining the single injector junction being such that said injector junction has substantially the same injection efficiency in both said hole injection mode and in said electron injection mode.
A semiconductor memory cell including
Floating gate injector memory cell comprising a single charge injector junction for injecting either electrons or holes onto the floating gate on application to the junction of a reverse bias at least equal to the avalanche threshold of that junction and means for controlling operation of the junction in an electron injection mode or in a hole injection mode, said floating gate overlying said charge injector junction and separated therefrom by a thin isolating layer, the control means comprising an address transistor and a read transistor both connected to the injector junction, wherein the read transistor has a thick gate isolating layer and a high threshold voltage, the read transistor having a channel located between said charge injection junction and capacitor means for coupling a bias voltage to said floating gate.
A semiconductor memory cell including a semiconductor substrate of one conductivity type, a floating gate conductor overlying said substrate and separated therefrom by an electrical isolating layer, combined hole and electron injector means defined by a single pn junction located in said substrate under said floating gate for selective operation in avalanche breakdown for alternatively injecting electrons or holes onto said gate, and control means for selectively applying operating voltages across said single injector junction means and to said floating gate for operating said single injector means in an electron injector mode or in a hole injector mode, wherein said single injector pn junction is an abrupt junction defined by a first region having an opposite conductivity from that of the substrate and a second region having the same conductivity type as but greater impurity concentration that that of said substrate such that said single injector means has substantially the same injection efficiency when operated in said hole injector mode as in said electron injection mode;
A semiconductor memory cell including a monocrystalline semiconductor substrate of one conductivity type, a floating gate conductor overlying said substrate and separated therefrom by a thin isolating layer, a combined hole and electron injector means having a single junction means defined by semiconductor regions of opposite conductivity types occupying laterally extending regions of said substrate beneath said floating gate conductor and defining between them a single pn junction means extending into the substrate transversely of the floating gate conductor for selective operation in avalanche breakdown for alternatively injecting holes or electrons onto said gate, and control means for selective operation of said single junction means in a hole injection mode or in an electron injection mode including means connected to said semiconductor regions for applying a voltage across said region to bias said single junction at least to avalanche breakdown threshold and means for selectively capacitively coupling a bias voltage to said floating gate;
A semiconductor memory cell including
Dependencies are inferred from the claim text.
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No related US applications are recorded in the indexed filing history.
Comprising cells containing floating gate transistors: comprising cells containing a single floating gate transistor and one or more separate…
Programmed by hot carrier injection: using hot carriers produced by avalanche breakdown of PN junctions, e.g. floating gate avalanche injection…
Static stores
Inorganic electric semiconductor devices
Term ended 7 Sep 1999 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
The present invention relates to memory cells and more particularly to charge injector, floating gate memory cells. For example, electrically reprogrammable non-volatile memory cells.
One known type of charge injector, floating gate memory cell is disclosed in U.S. Pat. No. 4,037,242 issued July 19, 1977 and diagrammatically illustrated by FIG. 1 herein. The memory cell has two charge injectors and comprises an aluminum floating gate 21 intended to control an electron injector 2 and a hole injector 3. To the floating gate 1 there is also connected to read transistor 4, while to each of the injectors 2 and 3 is respectively connected an address transistor 5, 6. The gate electrode of the address transistor 6 is connected to the floating gate by a coupling capacitor 7. The source electrodes of the address transistors 5 and 6 are connected to a terminal 8 for writing, erasing and reading the cell. The drain transistor for the read transistor 4 constitutes the read terminal of the cell. The cross-hatched regions of the cell shown in FIG. 1 are the regions in which the floating gate 1 is only separated from the substrate by a thin (e.g. about 1,000 Angstroms) isolating layer, typically of silicon dioxide. This known memory cell functions in the following manner.
During the write operation, the address transistor 5 only is made conductive and the diode 2 forming the electron injector and constituted by a p+/n junction is biased into avalanche by application to the terminal 8 of a potential more negative than the breakdown potential. Under these conditions, hot electrons generated by avalanche breakdown are injected through the thin oxide layer onto the floating gate 1 which also is charged to a negative potential. During this operation, the terminal 9 of the read transistor is maintained floating.
Other characteristics of the invention will appear in the course of the following description, given by way of example only, of illustrative embodiments described with reference to the drawings in which:
FIGS. 1 and 2 exemplifies prior art as described above;
FIG. 3 is a sectional view of an improved memory cell;
A memory cell structure according to an embodiment of one aspect of the present invention is shown in FIGS. 3 and 4. This cell comprises an n-type substrate 31 in the upper surface of which are formed a p+ doped region 32, a p type region 33 in contact with the region 32 and an n+ type region 34 contacting the region 33. Only the p type region 33 is produced by ion implantation while the n+ type region is produced by thermal diffusion. The regions 33 and 34 thus define a combined electron and hole injector diode. This structure utilizes the recognition that to achieve efficient injection of electrons and holes, it is necessary to make the single injection diode assymetrical in terms of doping favoring hole injection, in order to compensate for hole mobility being less than that of electrons. The hole injection resulting from such a non-symmetrical n+/p junction structure of the double injector cell can be made as efficient for electron injection as the electron injector provided by the p+n diode of a conventional memory cell, such as illustrated by FIG. 1, employing separate hole and electron injector diodes.
The resultant structure is covered by a silicon dioxide layer 35 which includes a thin portion 36 above the junction 37 defined by the diode regions 33 and 34. A conductive floating gate 38 is disposed on the thin portion 36 of the silicon oxide layer 35. A contact element 39 on the oxide layer 35 provides a terminal to the region 32.
Injection of electrons or holes is selected according to the polarity of the electric field applied across the thin oxide layer 36, that is to say, by the voltage applied to the coupling capacitor 30 connected to the floating gate 38, this voltage being either zero or negative n in the case of the cell described with reference to FIG. 1. The cell described also includes a single address transistor 23 and a read transistor 24.