Self-limiting erasable memory cell with triple level polysilicon

A method of making an electrically erasable floating gate field effect transistor memory cell comprising the steps of:

• depositing a first layer of conductive material on a face of a silicon body to provide a floating gate which is over a channel region of said face between source and drain areas of said field effect transistor, and to provide an erase window laterally spaced from said channel region,
• depositing a second layer of conductive material on said face overlying said floating gate but insulated therefrom by a first insulator coating to provide a control gate, the control gate not overlying said erase window,
• depositing a third layer of conductive material on said face partially overlying the second layer and overlying said erase window but insulated therefrom by a second insulator coating, the second insulator coating differing from the first insulator coating by enhanced erase current through the second insulator coating relative to that through the first insulator coating.

A semiconductor device comprising first and second regions defined in a face of a body of semiconductor material, a first gate on said face between the first and second regions insulated from the semiconductor material by a gate insulator, a second gate overlying part of the first gate insulated therefrom by an interlevel insulator, a segment of the first gate laterally spaced from said second, conductive means on said face partially overlying said first gate and insulated therefrom by an insulating layer with a portion of the conductive means laterally spaced from said first gate overlying said segment of the first gate, an insulating coating on said segment separating the portion of the conductive means from said segment but permitting the first gate to discharge electrons into the conductive means.

A method of making a semiconductor device comprising the steps of:

• depositing a first layer of conductive material on a face of a semiconductor body to provide a first gate which is over a channel region of said face between first and second regions of said device, and to provide a window area laterally spaced on said face from said channel region,
• depositing a second layer of conductive material on said face overlying said first gate but insulated therefrom by a first insulator coating to provide a second gate,
• depositing a third layer of conductive material on said face partially overlying said second layer and overlying said window area but insulated therefrom by a second insulator coating, the second insulator coating differing from the first insulator coating.