Geometry for fabricating enhancement and depletion-type, pull-up field effect transistor devices

An integrated circuit comprising:

• a substrate of semiconductor material of a first conductivity type;
• a field effect transistor formed in said substrate, including a channel diffusion region, a source diffusion region, and a drain diffusion region;
• and
• a polysilicon layer disposed on said substrate, said layer including a first portion forming the gate electrode of said field effect transistor, a second portion electrically connected to said first portion, said entire second portion overlapping and directly electrically connected to a portion of said source diffusion region, said first portion including a first edge substantially adjacent said drain diffusion region forming one end of said channel region of said field effect transistor, and a second edge substantially adjacent said source diffusion region forming the other end of said channel region, said second edge being spaced from said second portion, and a third portion electrically connecting said first portion and said second portion, said third portion being disposed on said substrate so that the normal projection of said third portion on the plane of said substrate lies entirely within said channel diffusion region.