US 4,300,279 AGranted

Method for the manufacture of a monolithic, static memory cell

AssigneeSiemens Aktiengesellschaft

InventorArmin Wieder

Life of this patent

Estimating the term…

Loading patent…

Abstract

Production of high bit density memory cells using six selective, vertically aligned, reactive plasma etching steps. A gate oxide layer is applied to the boundary surface of the semiconductor layer and has a polysilicon layer which is highly doped and covered with a first intermediate oxide layer. A drive line and the gate are first formed. Sections of the drive line at the ends thereof are removed by isotropic etching and the resulting recesses are filled in a thermal oxidation step. The portion of the gate oxide layer adjacent the structured parts is removed by a second etching step. A second polysilicon layer is deposited, highly doped and covered with a second intermediate oxide layer. Another drive line having a part contacting a doped region in the semiconductor layer, the region being formed by ion implantation, is structured by a third etching step. A recess is then formed by a fourth etching step and an isotropic etching step is performed to remove those parts of the drive line which extend to the last-mentioned recess. A fifth etching step is performed for removing the oxide layer covering the boundary surface of the semiconductor layer within the recess. A third, silicon layer is deposited and covered with a third intermediate oxide layer. Another recess is formed in the third intermediate oxide layer above the recess provided by the fourth etching in a sixth etching step. A conductive coating is then applied to the third polysilicon layer and is provided with an electrical terminal.

A method of manufacturing a monolithic, static memory cell in which a semiconductor body of a first conductivity type carries a semiconductor layer of a second, opposite conductivity type, in which the semiconductor layer includes a region therein at its boundary surface of the first conductivity type and a first drive line connected to the region and to a second terminal, in which a gate connected to a third terminal is separated from the semiconductor layer by an insulating layer, in which the gate is located adjacent to a first zone in the semiconductor layer, in which a conductive coating separated from the semiconductor layer by a thin insulating layer admitting a tunnel current between the boundary surface and the conductive coating is located over a second zone of the semiconductor layer, in which the conductive coating is connected to a fourth terminal, comprising the steps of:

(a) forming boundaries defining the extent of the memory cell in the semiconductor layer;
(b) applying a gate oxide layer on the boundary surface of the semiconductor layer;
(c) applying a highly-doped first polycrystalline layer on the gate oxide layer.
(d) applying a first intermediate oxide layer on the polycrystalline layer;
(e) etching the structure to form a gate and a second drive line;
(f) etching the ends of the second drive line to form recesses;
(g) filling the recesses with an insulating material;
(h) removing the gate oxide layer adjacent the structured portions;
(i) applying a highly-doped second polycrystalline silicon layer on the first intermediate oxide layer;
(j) applying a second intermediate insulating layer on the second polycrystalline silicon layer;
(k) etching the first drive line contacting the region to structure the same;
(l) ion implanting to dope the region contacting the first drive line;
(m) etching to form a recess down to the boundary surface of the semiconductor layer;
(n) etching portions of the first and second drive lines which extend into the recess of step (m);
(o) oxidizing the bottom of and the sides of the recess of step (m) to fill the voids left in the step (n);
(p) etching the oxide formed in the bottom of the recess of step (o) to remove the same;
(q) applying a third polycrystalline layer;
(r) applying a third intermediate layer on the third polycrystalline layer;
(s) etching an aligned recess through the third polycrystalline and third intermediate insulating layers;
(t) applying a conductive coating in the aligned recesses;
and
(u) applying a terminal to the conductive coating.

19 more elements

Abstract

Claims19