Taper isolated random access memory array and method of operating
AssigneeTexas Instruments Incorporated
InventorsPallab K. Chatterjee, Geoffrey W. Taylor
Life of this patent
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Abstract
The present invention is embodied in a method of operating a dynamic random access memory (RAM) array having individual depletion mode metal-oxide-semiconductor (MOS) transistors as the memory cells. The cells can be programmed to two threshold states providing constant current sensing. Cell programming is by application of appropriate signals to the transistor gate electrode and source. Reading is accomplished by grounding the source and sensing current through the transistor. An intermediate voltage on the gate electrode prevents changes in the state of the cell.
Claims8
A method of operating an X-Y array of semiconductor random access memory cells by writing information into, storing information in, and reading information out of a single cell in the array without disturbing the state of other cells in the array, wherein each memory cell has a single depletion mode, buried channel, metal-oxide-semiconductor transistor with a source, drain, and gate, the array being arranged in rows and columns of memory cells, all the drains in each column of the array being connected to a Y-read line for that column, all the sources in each row of the array being connected to an X-select line for that row, and all the gates in each column of the array being connected to a Y-write line for that column, said method comprising:
- applying appropriate signals to a particular X-select line and a particular Y-write line, and sensing the signal on a Y-read line corresponding to the selected single cell while maintaining the potential at a high reference voltage magnitude V.sub.DD on all other X-select lines and while maintaining the potential at an intermediate voltage magnitude V.sub.GG less than V.sub.DD but greater than a low reference voltage magnitude V.sub.SS on all other Y-write lines.
A random access memory device comprising:
- a substrate of a semiconductor material of a first conductivity type;
- an array of insulated gate field effect transistors as memory cells arranged in an X-Y matrix of rows and columns on said substrate;
- each memory cell including
- a pair of spaced doped regions in said substrate extending to a surface thereof and being of the opposite conductivity type, said doped regions forming a source and drain of a transistor,
- a buried doped region of said opposite conductivity type disposed wholly below the surface of said substrate and extending between and interconnecting said source and drain,
- a surface region of said first conductivity type defined along said surface of said substrate and disposed directly above said buried doped region, said surface region of said first conductivity type being in contact with said buried doped region and extending between said source and drain,
- a gate insulation layer upon said surface of said substrate and extending between said source and drain in overlying relation to said surface region of said first conductivity type, and
- a conductive member upon said gate insulation layer and forming the gate electrode of the transistor;
- said gate electrodes in each one of one of said rows and columns of the X-Y matrix being included in a common first conductive strip and forming a write line such that a plurality of first conductive strips forming write lines corresponding to the said one of said rows and columns are provided;
- said drains of said memory cells included in each of the said one of said rows and columns of the X-Y matrix being defined by a common doped region and forming a read line for each of the said one of said rows and columns;
- an insulating layer disposed on said plurality of first conductive strips forming the gate electrodes of the transistors included in the X-Y matrix and having a plurality of apertures in registration with said sources of said transistors;
- and
- a plurality of second conductive strips disposed on said insulating layer and respectively covering the apertures of each of said sources included in a common one of the other of said rows and columns and electrically contacting said sources to form a plurality of select lines respectively corresponding to each of the said other of said rows and columns;
- means for applying a first voltage V.sub.SS to a particular select line corresponding to a selected single cell in the write and read modes of operation;
- means for alternatively applying said first voltage V.sub.SS or a second voltage V.sub.DD higher than said first voltage V.sub.SS to a particular write line corresponding to said selected single cell in the write mode depending upon whether a binary "1" or a "0" is to be written into said selected single cell;
- means for applying a third voltage V.sub.GG intermediate in magnitude to said first voltage V.sub.SS and said second voltage V.sub.DD to said particular write line corresponding to said selected single cell in the read mode and in the store mode;
- means for applying said second voltage V.sub.DD to said particular select line corresponding to said selected single cell in the store mode;
- and
- means for maintaining said second voltage V.sub.DD on the remaining select lines and said third voltage V.sub.GG on the remaining write lines to retain all of the memory cells of said array other than said selected single cell in their present state.
Dependencies are inferred from the claim text.