Dual gate controlled thyristor with highly doped cathode base grid covered with high resistivity base layer

A gate controlled semiconductor device comprising:

• a semiconductor wafer made of:
• a first layer of one conductivity type;
• a second layer of an opposite conductivity type, connected to the first layer;
• a third layer of said one conductivity type connected to said second layer;
• said first and third layers having exposed surfaces;
• a high resistance layer of said one conductivity type formed on said third layer at said surface thereof to a selected depth;
• and a fourth layer of said second conductivity type connected into said high resistance layer having a surface;
• an anode electrode connected to said first layer exposed surface;
• a cathode electrode connected to said fourth layer surface;
• a first gate electrode layer connected to an exposed surface of said high resistance layer;
• said third layer having a first slot in the exposed surface thereof;
• a first low resistance layer at the bottom of said first slot;
• said third layer having a plurality of second slots extending into said fourth layer and communicating with said first slot;
• a second low resistance layer at the bottom of each of said plurality of second slots connected to said first low resistance layer;
• a second gate electrode layer for supplying an OFF signal to the device connected over a surface of said first and second low resistance layers;
• and
• at least one buried low resistance layer which is narrower than said first and second low resistance layers;
• embedded in said third layer and spaced from said second and fourth layers, connected to each of said second low resistance layers.