Integrated logic gate with NPN inverter, PNP clamp, coupling, Shottky diodes and diffused crossunder

A logic element structure suitable for high density integration comprising:

• a first NPN transistor having a base coupled to an input terminal of said logic element, an emitter coupled to circuit ground and a collector;
• at least one Schottky diode coupled to said collector of said first NPN transistor and forming an output of said logic element structure;
• and
• a second PNP anti-saturation transistor having a base coupled to said collector of said first transistor, a collector coupled to circuit ground and an emitter coupled to said base of said first transitor;
• said logic element being formed as a monolithic integration on a semiconductor crystal and comprising:
• a substrate;
• a first region of N.sup.+ -type semiconductor material at least partially buried within said substrate;
• an insulating wall of P-type conductivity in contact with said substrate;
• an isolated region of N-type semiconductor material having a generally rectangular solid shape including inner and outer principal faces and lateral faces, said region being bounded on its inner principal face by said substrate and by said buried layer and being bounded on its lateral faces by said insulting wall;
• a first zone of P-type semiconductor material disposed on the outer principal face of said isolated region and partly covering said insulating wall;
• a second region of P-type semiconductor material disposed on the outer principal face of said isolated region and insulated from said first P-type region of semiconductor material by a portion of said N-type isolated region;
• a second region of N.sup.+ -type semiconductor material diffused within said second P-type semiconductor region;
• and
• a third N.sup.+ -type semiconductor region diffused into the insulating wall providing connection to an adjacent logic element;
• the Schottky diode being formed on the principal outer face of said isolated region between said two P-type regions.

An integrated circuit, comprising:

• a plurality of logic elements, each such logic element comprising:
• a first NPN transistor having an emitter coupled to circuit ground, a collector and a base;
• a Schottky diode coupled to said collector of said first transistor for providing a logic element output;
• and
• a second PNP anti-saturation transistor having a base coupled to said collector of said first transistor, a collector coupled to circuit ground and an emitter coupled to said base of said first transistor;
• said first and second transistors together comprising an isolated region of N-type semiconductor material having a generally rectangular solid shape including inner and outer principal faces and lateral faces, said region being bounded on its inner principal face by a substrate and by a buried layer of N.sup.+ -type semiconductor material, said isolated region being bounded on its lateral faces by an insulating wall of P-type semiconductor material and being bounded on its principal outer face by a first a first region of P-type semiconductor material, this first region of P-type semiconductor material occupying the periphery of the isolated region and partially covering the insulating wall, said isolated region also being bounded on its principal outer face by a second region of P-type semiconductor material insulated from the first region of P-type semiconductor material by a minimum thickness of N-type seminconductor material, this second region of P-type semiconductor material surrounding a second region of N.sup.+ -type semiconductor material, and
• said Schottky diode comprising and being formed by a metallisation on the principal outer face of the isolated region between the first and second P-type semiconductor regions;
• and
• an N.sup.+ -type semiconductor region, of the same nature as the emitter of the NPN transistor, diffused into the insulating wall separting two adjacent logic elements, said diffused N.sup.+ -type semiconductor region providing connections between said two adjacent logic elements through the wall, thereby enhancing integration density.

An integrated circuit, comprising:

• a plurality of logic elements, each logic element comprising
• a first NPN transistor having a base coupled to an input terminal of said logic element, an emitter coupled to circuit ground and a collector;
• at least one Schottky diode coupled to said collector of said first NPN transistor and forming an output of said logic element structure;
• and
• a second PNP anti-saturation transistor having a base coupled to said collector of said first transistor, a collector coupled to circuit ground and an emitter coupled to said base of said first transistor;
• said transistors comprising a substrate;
• a first region of N.sup.+ -type semiconductor material at least partially buried within said substrate;
• an insulating wall of P-type conductivity in contact with said substrate;
• and isolated region of N-type semiconductor material having a generally rectangular solid shape including inner and outer principal faces and lateral faces, said region being bounded on its inner principal face by said substrate and by said buried layer and bounded on its lateral faces by said insulating wall;
• a first zone of P-type semiconductor material disposed on the outer principal face of said isolated region and partly covering said insulating wall;
• a second region of P-type semiconductor material disposed on the outer principal face of said isolated region and insulated from said first P-type region of semiconductor material by a portion of said N-type isolated region;
• a second region of N.sup.+ -type semiconductor material diffused within said second P-type semiconductor region;
• and wherein
• the Schottky diode is formed on the principal outer face of said isolated region between said two P-type regions;
• and
• an N.sup.+ -type semiconductor region, of the same nature as the emitter of the NPN transistor, diffused into the insulating wall separating two adjacent logic elements, said diffused N.sup.+ -type semiconductor region providing connections between said two adjacent logic elements through the wall, thereby enhancing integration density.