Complementary metal-oxide semiconductor
AssigneeFujitsu Limited
InventorsHideo Kikuchi, Haruyoshi Takaoka, Shigenori Baba
Life of this patent
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Abstract
A complementary metal-oxide semiconductor comprises at least one P channel MOSFET and at least one N channel MOSFET. In the semiconductor at least one additional doped portion is formed close to at least one of the P and N channel MOSFETs at a small part of the region which is driven by the voltage supply. The additional doped portion is directly connected to the voltage supply.
Claims13
In a field effect transistor device which includes a first portion of a substrate having a first type of conductivity, a second portion of the substrate having a second type of conductivity opposite to the first conductivity type and being contained in the first substrate portion, at least one first channel field-effect transistor formed in the second substrate portion and provided with two first regions each having the first conductivity type which act as the source and the drain thereof, at least one second channel field-effect transistor in the first substrate portion with two second regions each having the second conductivity type which act as the source and the drain thereof, a first voltage supply which applies a first voltage potential to the first substrate portion and to a selected one of said second regions of at least one of said second field-effect transistor(s) and a second voltage supply which applies a second voltage potential to the second substrate portion and to a selected one of said first regions of at least one of said first field-effect transistors, the configuration of selected ones of said two regions of each of said first and second substrate portions and said first and second substrate portions comprising at least one parasitic bipolar transistor, the improvement comprising:
- at least one additional doped portion in a respective selected one of said first and second substrate portions and having the same conductivity type as the respective substrate portion in which it is formed, formed at a position sufficiently close to a respective region of the respective field-effect transistor that is directly connected to the respective voltage supply so as to reduce effectively to zero the resistance biasing the base of said at least one parasitic bipolar transistor that is associated with the respective second region that is directly connected to the respective voltage supply, each said additional doped portion being directly connected to the respective voltage supply.
Dependencies are inferred from the claim text.