Topography for integrated circuit pattern recognition array

An integrated circuit for sequentially receiving a plurality of binary interval numbers each representing the width of a time interval occurring during optical scanning of a bar coded label, the integrated circuit receiving a plurality of signals each representing whether a respective one of the time intervals is a bar or a space, said integrated circuit comprising in combination:

• a. first means for receiving and storing said binary interval numbers;
• b. second means for adding predetermined ones of said stored binary interval numbers and storing the resulting sums;
• c. third means responsive to said first and second means for comparing predetermined ones of said sums and said stored resulting sums to produce a plurality of intermediate logic signals;
• d. fourth means responsive to said third means for encoding predetermined ones of said intermediate logic signals to produce a digital character number representing a character scanned on the bar encoded label;
• and
• e. output means for outputting said digital character number;
• said integrated circuit having first, second, third and fourth sequentially located edges, said first means being located substantially closer to said first edge than to said third edge to reduce lengths of conductors conducting signals representing said binary interval numbers from respective input pads which are located along said first edge, said third means being located substantially closer to said third edge than to said first edge, said second means being located generally between said first means and said third means to reduce capacitances of clock signal conductors which are distributed through said second means,
• said fourth means being located substantially closer to said fourth edge than to said second edge to reduce the lengths of said second and fourth edges, wherein said first means includes a plurality of bonding pads and input buffer means for receiving said binary interval numbers and first delay means coupled to said input buffer means for temporarily storing and delaying binary interval numbers received by said bonding pads, said first delay means being located between said input buffer means and said second means immediately adjacent to said input buffer means in order to avoid degradation of voltage of input signals transmitted from said input buffer means to said delay means,
• said integrated circuit including clock signal generating means for producing clock signals to be distributed to various portions of said integrated circuit and a metal power bus connected to a bonding pad, said metal power bus extending from a location adjacent to said first edge through said first means to said second means between upper and lower portions of said power means, said clock signals being conducted on metal conductors and diffused crossunders which pass beneath the portion of said metal power bus extending through said first means, the placement of said portion of said metal power bus extending through said first means being selected to avoid delay of certain of said clock signals to circuitry in each upper portion of said first means.