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US 4,284,998 AGranted
Junction type field effect transistor with source at oxide-gate interface depth to maximize .mu.
AssigneeTokyo Shibaura Electric Co., Ltd.
InventorsNoboru Fuse, Kenichi Muramoto, Keizo Tani, Masaaki Iwanishi
Life of this patent
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Abstract
A junction type field effect transistor comprises a semiconductor layer of one conductivity type acting as a drain region, a source region of said one conductivity type formed to a prescribed depth from the surface of the semiconductor layer, an insulation layer formed to a prescribed depth from the surface of the semiconductor layer to surround the source region, and a gate region of the opposite conductivity type formed in the proximity of the sorce region. The insulation layer and source region are formed to substantially the same depth.
Claims13
A junction type field effect transistor comprising:
- a drain region formed of a semiconductor layer of one conductivity type;
- a source region constituted by a first layer of said one conductivity type which is formed to a prescribed depth from the surface of the semiconductor layer at a high concentration of impurity;
- an insulation layer formed in the semiconductor layer closely around the source region, with said source region being sufficiently deep with respect to said insulation layer, at least from the surface of said semiconductor layer, to establish triode voltage-current characteristics, and said source region being formed sufficiently shallow with respect to said insulation layer, at least from the surface of said semiconductor layer, to maximize voltage-amplifying degree .mu.;
- and
- a gate region constituted by a second layer of the opposite conductivity type to the semiconductor layer which is formed in the semiconductor layer to a prescribed depth from the underside of the insulation layer so as to extend from the proximity of the source region away from the source region.
2 more elements
A junction type field effect transistor comprising:
- a drain region formed of an N-type semiconductor layer having an impurity concentration of 1.times.10.sup.14 to 1.times.10.sup.15 atoms/cm.sup.3 ;
- a source region constituted by an N-type layer formed to a depth of 5,000 to 7,000 A from the surface of the semiconductor layer at an impurity concentration of 5.times.10.sup.19 to 3.times.10.sup.20 atoms/cm.sup.3 ;
- an insulation layer surrounding the source region and formed in the semiconductor layer closely around the source region, with said source region being sufficiently deep with respect to said insulation layer, at least from the surface of the semiconductor layer, to establish triode voltage-current characteristics and said source region being formed sufficiently shallow with respect to said insulation layer, at least from the surface of the semiconductor layer, to maximize voltage-amplifying degree .mu.;
- and
- a gate region constituted by a P-type layer having an impurity concentration of 1.times.10.sup.19 to 5.times.10.sup.19 atoms/cm.sup.3 which is formed in the semiconductor layer to a prescribed depth from the underside of the insulation layer so as to be laterally displaced from said source region at least 1.3 microns and extending away from the source region to surround that portion of the semiconductor layer in which the source region is formed, and wherein a distance l between a first plane defined by the underside of the insulation layer and a second plane defined by the underside of the gate region is one to one and a half fold of a distance d between third and fourth planes which are parallel to each other and are perpendicular to said first and second planes, with said third and fourth planes intersecting a common junction of said drain region, gate region, and insulation layer on opposite sides of said source region.
2 more elements
A junction type field effect transistor comprising:
- a drain region formed of an N-type semiconductor layer having an impurity concentration of 1.times.10.sup.14 to 1.times.10.sup.15 atoms/cm.sup.3 ;
- a source region constituted by an N-type layer formed to a depth of 5,000 to 7,000 A from the surface of the semiconductor layer at an impurity concentration of 5.times.10.sup.19 to 3.times.10.sup.20 atoms/cm.sup.3 ;
- an insulation layer surrounding the source region and formed in the semiconductor layer closely around the source region to the same depth as the source region at least from the surface of the semiconductor layer;
- and
- a gate region constituted by a P-type layer having an impurity concentration of 1.times.10.sup.19 to 5.times.10.sup.19 atoms/cm.sup.3 which is formed in the semiconductor layer to a prescribed depth from the underside of the insulation layer so as to be laterally displaced from said source region at least 1.3 microns and extending away from the source region to surround that portion of the semiconductor layer in which the source region is formed and wherein a distance l between a first plane defined by the underside of the insulation layer and a second plane defined by the underside of the gate region is one to one and a half fold of a distance d between third and fourth planes which are parallel to each other and are perpendicular to said first and second planes, with said third and fourth planes intersecting a common junction of said drain region, gate region, and insulation layer on opposite sides of said source region.
2 more elements
Dependencies are inferred from the claim text.