Static induction transistor and its applied devices

A semiconductor device formed in a semiconductor body having first and second parallel principal surfaces and including at least one vertical current channel at which a main current is substantially controlled and at which charge carriers constituting said main current are allowed to flow substantially perpendicular to said principal surfaces, comprising:

• at least one channel semiconductor region disposed in said semiconductor body to form said at least one current channel therein;
• a source semiconductor region for supplying said charge carriers into said channel semiconductor region, disposed at one end of said channel semiconductor region;
• at least one drain means for retrieving said charge carriers from said channel semiconductor region, disposed at the other end of said channel semiconductor region;
• and
• means for controlling the potential profile in said channel semiconductor region to define said current channel, including a first gate means and a second gate means disposed adjacent to a same portion of said channel semiconductor region and separated from each other,
• said current channel being defined at said portion in said channel semiconductor region partially by said first gate means and partially by said second gate means,
• said first gate means being adapted to be connected to a signal source for developing, in said channel semiconductor region, a depletion region with a width depending on a controlling signal supplied from said signal source,
• and said second gate means being electrically connected to said source semiconductor region.

A semiconductor device formed in a semiconductor body having first and second parallel principal surfaces and including at least one vertical current channel at which a main current is substantially controlled and at which charge carriers constituting said main current are allowed to flow substantially perpendicular to said principal surfaces, comprising:

• at least one channel semiconductor region disposed in said semiconductor body to form said at least one current channel therein;
• a source semiconductor region for supplying said charge carriers into said channel semiconductor region, disposed at one end of said channel semiconductor region;
• at least one drain means for retrieving said charge carriers from said channel semiconductor region, disposed at the other end of said channel semiconductor region;
• and
• means for controlling the potential profile in said channel semiconductor region to define said current channel, including a first gate means and a second gate means disposed adjacent to a same portion of said channel semiconductor region and separated from each other,
• said current channel being defined at said portion in said channel semiconductor region partially by said first gate means and partially by said second gate means,
• said first gate means being adapted to be connected to a signal source for developing, in said channel semiconductor region, a depletion region with a width depending on a controlling signal supplied from said signal source, and
• said second gate means being electrically isolated from each of said source semiconductor region, said means for retrieving said charge carriers and said first gate means.

A semiconductor memory device formed in a semiconductor body and including at least one memory cell, said memory cell comprising:

• a source region having a source potential associated therewith;
• a storage region;
• a channel semiconductor region disposed between said source region and said storage region and providing a path of charge carriers therebetween;
• split gate regions including a first gate region and a second gate region disposed adjacent to a same portion of said channel region and jointly defining a channel in said channel region;
• said first gate region being adapted to respond to a controlling signal;
• said second gate region being adapted to receive a dc bias voltage;
• and
• said source, channel, storage and split gate regions being disposed in said semiconductor body, and said channel region being capable of establishing a potential barrier under control of at least said source potential and said first gate controlling signal.

A semiconductor memory device formed in a semi conductor body and including at least one memory cell, said memory cell comprising:

• a source region having a source potential associated therewith;
• a storage region;
• a channel semiconductor region disposed between said source region and said storage region and providing a path of charge carriers therebetween;
• and
• split gate regions including a first gate region and a second gate region disposed adjacent to a same portion of said channel region and jointly defining a channel in said channel region;
• said first gate region being adapted to be given a controlling signal;
• said second gate region being electrically floated;
• and
• said source, channel, storage and split gate regions being disposed in said semiconductor body, and said channel region being capable of establishing a potential barrier under control of at least said source potential and said first gate controlling signal.

A semiconductor memory device formed in a semiconductor body and including at least one memory cell, said memory cell comprising:

• a source region having a source potential
• associated therewith;
• a storage region;
• a channel semiconductor region disposed between said source region and said storage region and providing a path of charge carriers therebetween;
• and
• split gate regions including a first gate region and a second gate region disposed adjacent to a same portion of said channel region and jointly defining a channel in said channel region;
• said first gate region being adapted to be given a controlling signal;
• and
• said second gate region being electrically floated;
• said source, channel, storage and split gate regions being disposed in said semiconductor body, and said channel region being capable of establishing a potential barrier under control of at least said source potential and said first gate controlling signal.

A semiconductor memory array, comprising:

• a semiconductor body;
• a plurality of bit lines and a plurality of word lines crossing each other;
• and at least one semiconductor memory cell disposed at one of cross points of said bit lines and said word lines, said semiconductor memory cell comprising:
• a source region having a source voltage associated therewith;
• a storage region;
• a channel region connecting said source and storage regions, and split gate regions including a first gate region and a second gate region disposed adjacent to a same portion of said channel region for establishing a potential barrier in said channel region, said first gate region being responsive to a controlling signal, said second gate region being responsive to a dc bias voltage, the height of said potential barrier being controllable by the voltages of said source region and said first gate region.

A semiconductor memory array, comprising:

• a semiconductor body;
• a plurality of bit lines and a plurality of word lines crossing each other;
• and at least one semiconductor memory cell disposed at one of cross points of said bit lines and said word lines, said semiconductor memory cell comprising:
• a source region having a source voltage associated therewith;
• a storage region;
• a channel region connecting said source and storage regions;
• and split gate regions including a first gate region and a second gate region disposed adjacent to a same portion of said channel region for establishing a potential barrier in said channel region, said first gate region being responsive to a controlling signal, and second gate region being electrically connected to said source region, the height of said potential barrier being controllable by the voltages of said source region and said first gate region.

A semiconductor memory array, comprising:

• a semiconductor body, a plurality of bit lines and a plurality of word lines crossing each other;
• and at least one semi conductor memory cell disposed at one of cross points of said bit lines and said word lines, said semiconductor memory cell comprising:
• a source region having a source voltage associated therewith;
• a storage region;
• a channel region connecting said source and storage regions;
• and split gate regions including a first gate region and a second gate region disposed adjacent to a same portion of said channel region for establishing a potential barrier in said channel region, said first gate region being responsive to a controlling signal, said second gate region being electrically floated;
• the height of said potential barrier being controllable by the voltages of said source region and said first gate region.

A semiconductor memory device formed in a semiconductor body and including at least one memory cell which comprises:

• a source region having a source voltage associated therewith;
• a storage region;
• a channel region disposed between said source and storage regions and providing a path of charge carriers therebetween;
• and
• split gate regions including a first gate region and a second gate region disposed adjacent to a same portion of said channel region for establishing a potential barrier in said channel region, said first gate region being responsive to a controlling signal, said second gate region being adapted to be given a dc bias voltage, the height of said potential barrier being controllable by the voltages of said source region and said first gate region.

A semiconductor memory device formed in a semiconductor body and including at least one memory cell which comprises:

• a source region having a source voltage associated therewith;
• a storage region;
• a channel region disposed between said source and storage regions and providing a path of charge carriers therebetween;
• and
• split gate regions including a first gate region and a second gate region disposed adjacent to a same portion of said channel region for establishing a potential barrier in said channel region, said first gate region being responsive to a controlling signal, said second gate region being electrically connected to said source region, the height of said potential barrier being controllable by the voltages of said source region and said first gate region.

A semiconductor device formed in a semiconductor body and including at least one memory cell which comprises:

• a source region having a source voltage associated therewith;
• a storage region;
• a channel region disposed between said source and storage regions and providing a path of charge carriers therebetween;
• and
• split gate regions including a first gate region and a second gate region disposed adjacent to a same portion of said channel region for establishing a potential barrier in said channel region, said first gate region being responsive to a controlling signal, said second gate region being electrically floated, the height of said potential barrier being controllable by the voltages of said source region and said first gate region.

In a semiconductor device of the type including source, drain, and channel semiconductor regions, in predetermined disposition to a principal surface said source drain and channel semiconductor regions being of a first conductivity type and relatively disposed in a semiconductor body to define a current path between said source and drain regions through said channel region, and further including gate means, responsive to a control signal applied thereto, for controllably generating a depletion layer extending into said channel region to control current flow through said current path in accordance with said control signal, the improvement wherein:

• said current path being generally perpendicular to said principal surface;
• said gate means comprises firt and second gate semi conductor regions of a second conductivity type opposite to said first conductivity type, each disposed in said semi conductor body separate from the other, adjacent to a common portion of said channel region;
• said first and second gate regions cooperating to control current flow along said path through said common portion of said channel region, with each said first and second gate region being electrically separated from the other, and with only said first gate region being responsive to said control signal and said second gate region being adapted to generate a depletion layer extending into said common portion of said channel region independently of said control signal.

A semiconductor memory device formed in a semiconductor body having a principal surface comprising:

• a source semiconductor region,
• a storage semiconductor region
• a channel semiconductor region, said channel semiconductor region being disposed in said semiconductor body between said source and storage regions and providing a charge carrier path therebetween, said path being generally perpendicular to said principal surface and
• gate means, disposed in said semiconductor body and responsive to a control signal applied thereto, for generating a depletion layer extending into a portion of said channel region for controlling the flow of charge carriers through said channel portion along said paths in accordance with said control signal;
• said gate means comprising first and second gate semiconductor regions each disposed separated from the other and adjacent to said portion of the channel region;
• each said first and second gate regions being electrically separated from the other, and adapted to generate independent depletion layers extending into said portion of said channel region, said first gate region depletion layer being in accordance to said control signal, and said second gate region depletion layer being independent of said control signal.

In a semiconductor device of the type including source, drain and channel semiconductor regions of a first conductivity type said source drain and channel semiconductor regions being relatively disposed in a semiconductor body to define a current path between said source and drain regions through said channel region, said current path being generally perpendicular to a principal surface of said semiconductor body said device further including gate means, responsive to a control signal applied thereto, for controllably generating a depletion layer extending into said channel region in accordance with said control signal to control current flow along said current path, the improvement wherein said gate means comprises:

• a first semiconductor region of a second conductivity type opposite to said first conductivity type, disposed adjacent to a portion of said channel region, and generating a depletion layer extending into said channel region portion in accordance with said control signal;
• and
• means for reducing gate capacitance and minority carrier storage effect in said device, said means for reducing comprising a second gate semiconductor region disposed separated from said first gate region adjacent to said channel region portion, said second gate region being electrically separated from said first gate region, and adapted to generate a depletion layer extending into said channel region portion, independently of said control signal, said first and second gate regions cooperating to control current flow through said channel portion.