Charge domain filter with single transmission zero

In combination,

• a substrate of semiconductor material of one conductivity type having a major surface,
• means forming a plurality of N charge storage cells adjacent said major surface of said substrate, each storage cell including a first electrode and a second electrode, said first and second electrodes insulatingly overlying said storage cell, said first electrode and said substrate forming a first capacitor having a first capacitance, said second electrode and said substrate forming a second capacitor having a second capacitance,
• a first shift register formed in said substrate having N serial coupled stages, each stage including a respective first charge storage region in said substrate underlying a respective one of said first electrodes,
• a second shift register formed in said substrate having N serial coupled stages, each stage including a respective first charge storage region in said substrate,
• first means for sequentially transferring packets of charge at one frequency from first charge storage region to first charge storage region of the stages of said first shift register,
• second means for sequentially transferring packets of charge at said one frequency from first charge storage region to first charge storage region of the stages of said second shift register,
• means for providing a first sequence of packets of charge, each packet representing a respective sample of an input signal, successive packets occurring at said one frequency,
• means for dividing each of said packets of charge of said first sequence into a first part and a second part, the ratio of said first part to said second part being equal to a first fixed value,
• means for applying sequentially each of said first parts of said packets of said first sequence to the first stage of said first shift register and for applying sequentially each of said second parts of said packets of said first sequence to the first stage of said second shift register,
• a plurality of combining means, each for combining the charge packet in the first charge storage region of a respective stage of said first shift register with the charge packet in an associated second charge storage region and for dividing the combined packet of charge into two portions over one part of a cycle of said first charge transferring means, a first portion of said combined packet being stored in the first charge storage region of a stage of said first shift register and a second portion of said combined pocket being stored in the second charge storage region associated therewith, the ratio of said first portion of charge to the combined packet of charge being equal to a second fixed value, said second fixed value being equal to the ratio of said first capacitance of the sum of said first capacitance and said second capacitance,
• the frequency response of each of the stages of said first shift register decreasing as the frequency of the input signal thereto increases and the shift in phase of the frequency response of each of the stages of said first register increasing as the frequency of the input signal thereto increases,
• said second fixed value providing a phase shift at a predetermined angular frequency .omega..sub.z which is equal to .pi. radians divided by an integer, said integer being equal to N, the number of stages in said first and second shift registers,
• said first fixed value being equal to ##EQU11## where .vertline.H.sub.N (.omega..sub.z).vertline. is the absolute magnitude of the amplitude response of N cascaded stages of said first shift register at said predetermined angular frequency .omega..sub.z,
• means for combining the output of the last stage of said first shift register with the output of the last stage of said second shift register, whereby a resultant output is obtained having zero amplitude at angular frequency .omega..sub.z.