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US 4,244,000 AGranted
PNPN Semiconductor switches
AssigneesNippon Telegraph & Telephone Public Corporation, Oki Electric Industry Co., Ltd.
InventorsJun Ueda, Haruo Mori, Kazuo Hagimura, Kotaro Kato
Life of this patent
Estimating the term…
Abstract
A circuit for preventing a dV/dt erroneous operation of a PNPN semiconductor switch is replaced by a capacitance on the surface of a semiconductor substrate, a high resistance gate electrode. In other words, such a circuit is formed on the surface of the substrate by a slight modification of the basic design without decreasing the chip area and without isolating component elements.
Claims10
A PNPN semiconductor switch comprising:
- (a) an N conductivity type semiconductor substrate,
- (b) a P conductivity type P gate region,
- (c) a P conductivity type anode region formed in said semiconductor substrate at a position which is a predetermined distance from said P gate region,
- (d) an N conductivity type cathode region formed in said P gate region,
- (e) an N conductivity type drain region formed in said P gate region at a position which is spaced from said N conductivity type cathode region,
- (f) a first insulating layer formed on the surface of said substrate between said cathode region and said drain region,
- (g) a first gate electrode formed on said first gate insulating layer,
- (h) a second gate insulating layer formed on said first gate electrode,
- (i) a third insulating layer formed on the surface of said substrate between said anode region and said P gate region,
- (j) a P gate electrode electrically connected to said drain region and said P gate region,
- (k) a resistance region connected between said first gate electrode and said P gate electrode,
- (l) a second gate electrode mounted on said second gate insulating layer,
- (m) a cathode electrode electrically connected to said cathode region, and
- (n) an anode electrode electrically connected to said anode region.
11 more elements
A bidirectional PNPN semiconductor switch comprising:
- (a) an N type semiconductor substrate,
- (b) a first P gate region of P type conductivity formed in said N type substrate,
- (c) a first anode region formed in said substrate at a position which is a predetermined distance apart from said first P gate region,
- (d) a first cathode region of N conductivity type formed in said first P gate region,
- (e) a first drain electrode formed in said first P gate region at a position which is a predetermined distance apart from said first cathode region,
- (f) a first gate insulating layer disposed on the surface of said substrate between said first cathode region and said first drain region,
- (g) a first gate electrode disposed on said first gate insulating layer,
- (h) a second gate insulating layer disposed on said first gate electrode,
- (i) a first insulating layer mounted on the surface of said substrate between said first anode region and said first P gate region,
- (j) a first P gate electrode electrically connected to said first drain region and said first P gate region,
- (k) a first resistance region electrically connected between said first gate electrode and said first P gate electrode,
- (l) a second gate electrode mounted on said second gate insulating layer,
- (m) a first cathode electrode electrically connected to said first cathode electrode,
- (n) a first anode electrode electrically connected to said first anode electrode,
- (o) a second P gate region formed in said substrate at a position which is a predetermined distance apart from said first P gate region,
- (p) a second anode region of P conductivity type formed at a position of said substrate which is a predetermined distance apart from said second P gate region,
- (q) a second cathode region of N conductivity type formed in said second P gate region,
- (r) a second drain region of N conductivity type formed in said second P gate region at a predetermined distance apart from said second cathode region,
- (s) a third gate insulating layer mounted on the surface of said substrate between said second substrate and said second drain region,
- (t) a third gate electrode mounted on said third gate electrode layer,
- (u) a fourth gate electrode layer mounted on said third gate electrode,
- (v) a second insulating layer formed on the surface of said substrate between said second anode region and said second P gate region,
- (w) a second P gate electrode electrically connected to said second drain electrode and said second P gate region,
- (x) a second resistance region electrically connected between said third gate electrode and said second P gate electrode,
- (y) a fourth gate electrode mounted on said fourth gate insulating layer,
- (z) a second cathode electrode electrically connected to said second cathode region,
- (A) a second anode electrode electrically connected to said second anode region, and
- (B) a third insulating region formed on the surface of said semiconductor substrate between said first P gate region and said second P gate region.
25 more elements
Dependencies are inferred from the claim text.