Clock system having a dynamically selectable clock period

A clock system comprising:

• (a) first means, having a first output, a first input, and a clock output, for generating a first signal having a first state and a second state at said first output, said first means for receiving a second signal having a third state and a fourth state at said first input, said first means for generating a clock signal having a fifth state and a sixth state at said clock output, said clock signal producing a series of clock cycles, each of said clock cycles having a first portion, having said fifth state for a duration substantially equal to a first time period and having a second portion having said sixth state for a duration substantially equal to a second time period;
• (b) second means having a second input and a second output, said second input coupled to said first output of said first means, said second means for generating at said second output one or more delayed first signals in response to said first signal received at said second input, each of said one or more delayed first signals having said first state and said second state, each of said one or more delayed first signals having an associated predetermined delay time period;
• (c) third means having a third input, a third output, and a fourth input, said third input coupled to said second output of said second means, said third output coupled to said first input of said first means, and fourth input for receiving a first selection signal, said first selection signal when in a predetermined state being operative to select one of said one or more delayed first signals, said third means including means for generating said second signal at said third output in response to said selected one of said one or more delayed first signals such that said second signal transitions to said third state before said first signal transitions from said first state to said second state, said third means including further means for enabling said second signal to remain in said third state after said first signal transitions to said second state for a time period substantially equal to the associated predetermined delay period of said selected one of said one or more delayed first signals;
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• (d) fourth means, included in said first means, for receiving said second signal at said first input, said fourth means operative to enable said first means to generate said second portion in response to said fourth state and to disable said first means to generate said second portion in response to said third state, whereby a change in said second signal from said third state to said fourth state enables for generation of said second portion of said clock cycles.

A method for generating a clock cycle having a time period of selectable predetermined duration which comprises:

• (a) generating a rectangular wave train through use of a generator having a first output, a first input, and a clock output, said first output for transmitting a first signal having a first state and a second state, said first input for receiving a second signal having a third state and a fourth state, said clock output for transmitting a clock signal having a fifth state and a sixth state, said clock signal producing a series of clock cycles each having a first portion and a second portion, said first portion being in said fifth state for a duration substantially equal to a first time period and said second portion being in said second state for a duration substantially equal to a second time period;
• (b) delaying said first signal by one or more predetermined delay time periods to produce one or more delayed said first signals;
• (c) synchronizing the generation of said delayed first signals during each one of said clock cycles such that each said delayed first signal transitions to a delayed first state, corresponding to said first state of said first signal, at a time when said first signal exists in said first state;
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• (d) feeding a selected one of said delayed first signals to said first input to supply said second signal such that the delayed first and second states of said selected delayed first signal correspond to the fourth and third states, respectively, of said second signal, said third state being operative to disable said generator from generating said second portion and said fourth state being operative to enable said generator to generate said second portion.