Power failure detection and restart system

A power failure detection system for use with a computer including in combination:

• first means for supplying a voltage to be monitored;
• second means for supplying a predetermined reference voltage;
• first comparator means having inputs coupled with said first and second means and having an output for supplying a first output signal level when a predetermined normal relationship exists between the voltages supplied by said first and second means and providing a second output signal level when a predetermined abnormal relationship exists between the voltages supplied by said first and second means;
• third means for supplying a second predetermined reference voltage;
• time delay circuit means;
• second comparator means having one input coupled with said third means, having a second input coupled with the output of said first comparator means through said time delay circuit means, and having an output for supplying a first output signal level when the output of said first comparator means is at said first output signal level and for supplying a second output signal level a predetermined time after the signal on the output of said first comparator changes from the first signal level to the second signal level;
• a battery protected memory;
• a microprocessor having registers therein, the output of said first comparator means producing a pulse to said microprocessor when the signal level on the output of said first comparator means changes from said first signal level to said second signal level, said pulse causing said microprocessor to interrupt operation and to store the status of predetermined ones of said registers in said memory response thereto, where the second signal level on the output of said second comparator means resets said microprocessor to a predetermined state of operation;
• timer circuit means coupled to said second comparator means for driving said second comparator means to produce the second output signal level on the output thereof in response to an output pulse of said timer circuit means produced a predetermined time after said timer circuit means is reset;
• and
• said microprocessor including means for supplying reset clock pulses to said timer circuit means at periodic intervals sufficient to reset said timer circuit means prior to said timer circuit means producing said output pulse thereof so long as the program operation of said microprocessor is correct.