Integrated logic circuit arrangement
AssigneeNippon Gakki Seizo Kabushiki Kaisha
InventorTerumoto Nonaka
Life of this patent
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Abstract
An integrated logic circuit arrangement comprising: an input junction field effect transistor having at least one source for receiving a digital input signal, a drain to which a load is connected, and gate held at a reference potential, said junction field effect transistor being operative to effect switching operation in accordance with said digital input signal; and an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain. This integrated logic circuit arrangement provides high speed logic operation, low power dissipation and high integration density.
Claims11
An integrated logic circuit arrangement comprising:
- an input junction field effect transistor having at least one source for receiving a digital input signal, a drain to which a load is connected, and a gate held at a fixed DC reference potential, said junction field effect transistor being operative to effect switching operation in accordance with said digital input signal, said load being adapted for connection between said drain and a power source;
- an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain;
- said output bipolar type transistor having a load connected to the emitter of said output bipolar transistor, whereby said output bipolar transistor behaves as an emitter-follower transistor;
- and
- a second emitter-follower transistor,
- the emitter of said output bipolar type transistor serving as the first mentioned emitter-follower transistor being connected to an emitter output terminal of said second emitter-follower transistor to thereby form a wired OR logic circuit.
An integrated logic circuit comprising:
- an input junction field effect transistor having at least one source for receiving a digital input signal, a drain to which a load is connected, and a gate, held at a reference potential, said junction field effect transistor being operative to effect switching operation in accordance with said digital input signal said load being connected between said drain and a power source;
- and
- an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain, the emitter of said output bipolar type transistor having a load connected thereto whereby said output bipolar transistor behaves as an emitter-follower transistor, wherein further the emitter of said output bipolar transistor is connected to an output terminal of another emitter-follower transistor to form a wired OR logic.
An integrated logic circuit comprising:
- an input junction field effect transistor having a plurality of sources, each receiving a respective digital input signal, a drain having a load connected thereto, and a gate held at a reference potential, said plural source junction field effect transistor being operative to effect switching operation in accordance with said digital input signal and an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain, whereby an AND logic is formed.
An integrated logic circuit arrangement comprising:
- an input junction field effect transistor having a plurality of sources for receiving digital input signals, a drain to which a load is connected, and a gate held at a fixed DC reference potential, said junction field effect transistor being operative to effect switching operation in accordance with said digital input signal, said plural sources forming an AND logic;
- and
- an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain.
Dependencies are inferred from the claim text.