US 4,231,055 AGranted

Complementary MOS transistors without an isolation region

AssigneeTokyo Shibaura Denki Kabushiki Kaisha

InventorTetsuya Iizuka

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Abstract

A first semiconductor region of P.sup.- type is formed in a semiconductor substrate of N.sup.- types. The N.sup.- region adjacent to the first semiconductor region is a second semiconductor region. A third semiconductor region of N.sup.+ type and a fourth semiconductor region of P.sup.+ type are formed on the first and second semiconductor regions, respectively. Between the first semiconductor region and fourth semiconductor region is formed a first channel region which includes a subregion of P.sup.- type and a fifth semiconductor region of N types. Between the second semiconductor region and third semiconductor region is formed a second channel region which includes a subregion of N.sup.- type and a sixth semiconductor region of P type. The fourth semiconductor region, the subregion of the first channel region and the sixth semiconductor region are used for a P-channel MOS transistor. The third semiconductor region, the subregion of the second channel region and the fifth semiconductor region are used for an N-channel MOS transistor.

Claims10

Dependent claims

A complementary metal-oxide-semiconductor (MOS) transistor comprising one of a semiconductor substrate and a semiconductor region provided on an insulating substrate, which includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type formed adjacent to said first semiconductor region;

a third semiconductor region of the second conductivity type provided on said first semiconductor region;
a fourth semiconductor region of the first conductivity type provided on said second semiconductor region;
a first channel region formed between said first semiconductor region and said fourth semiconductor region and having a subregion with a prescribed conductivity type having a specified impurity concentration;
a second channel region formed between said second semiconductor region and said third semiconductor region and having a subregion with a prescribed conductivity type having a specified impurity concentration;
a fifth semiconductor region of the second conductivity type provided in a portion of said first channel region and adjacent to the subregion of said second channel region;
a sixth semiconductor region of the first conductivity type formed in a portion of said second channel region and adjacent to the subregion of said first channel region;
and gate electrode means positioned above said first and second channel regions through an insulation layer for controlling said first and second channel regions;
an MOS transistor of the first channel type of said complementary MOS transistor including said fourth semiconductor region, the subregion of said first channel region and said sixth semiconductor region;
an MOS transistor of the second channel type of said complementary MOS transistor including said third semiconductor region, the subregion of said second channel region and said fifth semiconductor region.

6 more elements

A semiconductor memory device, which comprises a first metal-oxide-semiconductor (MOS) transistor of a second channel type, one terminal of which is connected to a first power source;

a third MOS transistor of a first channel type, one terminal of which is connected to a second power source;
a second MOS transistor of a second channel type which is connected between the other terminal of said first MOS transistor and the other terminal of said third MOS transistor;
and a fourth MOS transistor which is connected between the junction of said first and second MOS transistors and a bit line and whose gate electrode is connected to a word line, and in which the gate electrodes of said first and third MOS transistors are connected to the junction of said first and second MOS transistors and the gate electrode of said second MOS transistor is connected to said second power source, and wherein said first and third MOS transistors are made into a complementary MOS transistor without an isolation region between said two MOS transistors, said complementary MOS transistor comprising a semiconductor substrate including a first region of a first conductivity type and a second region of a second conductivity type which is set adjacent to said first region;
a third region of the second conductivity type which is formed on said first region;
a fourth region of the first conductivity type which is formed on said second region;
a first channel region formed between said first region and fourth region and having a subregion with a prescribed conductivity type having a specified impurity concentration;
a second channel region formed between said second region and third region and having a subregion with a prescribed conductivity type having a specified concentration;
a fifth region of the second conductivity type provided in a portion of said first channel region and adjacent to the subregion of said second channel region;
a sixth region of the first conductivity type formed in a portion of said second channel region and adjacent to the subregion of said first channel region;
and gate electrode means provided above said first and second channel regions through an insulation layer for controlling said first and second channel regions;
an MOS transistor of the first channel type of said complementary MOS transistor including said fourth region, the subregion of said first channel region and said sixth region;
an MOS transistor of the second channel type of said complementary MOS transistor including said third region, the subregion of said second channel region and said fifth region.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 05/957,443Filed 3 Nov 1978
Priority: JP 52/13764916 Nov 1977
Granted: 28 Oct 1980
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10W 10/30
Isolation regions in semiconductor bodies between components of integrated devices: isolation regions comprising PN junctions
H10D 84/858
Complementary IGFETs, e.g. CMOS: comprising a P-type well but not an N-type well
H10W 10/031
Manufacture or treatment: of isolation regions comprising PN junctions
H10W
Generic packages, interconnections, connectors or other constructional details of devices covered by