Multiple clock selection system
AssigneeData General Corporation
InventorJohn M. Frissell
Life of this patent
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Abstract
A system for switching among a plurality of input clock signals to produce an output clock signal which avoids the presence of spurious signals during the process of switching from one to another of said plurality of input clock signals. When it is desired to switch from one input clock signal to a new input clock signal, clock output logic is inhibited from supplying any clock output signal for a selected time period, after which the newly selected input clock signal is supplied as the clock output signal. The time period is dependent on the clock pulse rate of the newly selected input clock signal and is sufficiently long to assure that no spurious signals will occur thereafter.
Claims10
Clock signal selection circuitry comprising
- means for providing at least two input clock signals, each having a different clock rate;
- means for selecting one of said at least two input clock signals;
- means responsive to said selected input clock signal for supplying an output clock signal corresponding to said selected input clock signal;
- single delay means responsive to said selected input clock signal for inhibiting the supplying of said output clock signal for a selected time period after a different one of said at least two input clock signals has been selected by said selecting means;
- said output clock signal supplying means being responsive to a newly selected input clock signal for supplying, after said selected time period, an output clock signal corresponding to said newly selected input clock signal.
Dependencies are inferred from the claim text.